[PATCH v2 00/36] KVM: arm64: Introduce vGIC-v5 with PPI support

[Sascha Bischoff]

On Fri, 2025-12-19 at 15:51 +0000, Sascha Bischoff wrote:
> This is the second version of the patch series to add the virtual
> GICv5 [1] device (vgic_v5). Only PPIs are supported by this initial
> series, and the vgic_v5 implementation is restricted to the CPU
> interface, only. Further patch series are to follow in due course,
> and
> will add support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS.
> 
> The first version of this series can be found at [2].
> 
> The noteworthy changes since V1 of this series are:
> 
> 1. Added detection of implemented PPIs on a GICv5 host at boot time.
> 2. Added masking for PPIs that are presented to guests. Only PPIs
> with
>    owners and the SW_PPI (if present) are exposed.
> 3. Added trapping and masking for all guest writes to the writable
>    ICC_PPI_x_EL1 registers. The writes are masked with the subset of
>    PPIs exposed to the guest. This ensures that the guest cannot
>    discover PPIs that are not intentionally exposed to it.
> 4. Added an new UAPI to allow userspace to query which PPIs can be
>    driven via KVM_IRQ_LINE. For the time being, only the SW_ PPI is
>    exposed for guest control.
> 5. Interrupt type checks are now re-worked to be more readable and
>    scalable. Thanks, Marc.
> 
> I have addressed some, but alas not all (see below), review comments
> against v1 of the series. Thanks a lot Marc, Joey, and Lorenzo!
> 
> I'm posting V2 even though I've yet to address all review comments as
> I shall be out of office for the next 2 weeks. Therefore, I wanted to
> make sure that the latest version was available for anyone to take a
> look. Any outstanding and new comments will be addressed on my
> return.
> 
> The main outstanding changes are:
> 
> 1. Rework the PPI save/restore mechanisms to remove the _entry/_exit
>    from the vcpu, and instead use per-cpu data structures.
> 2. PPI injection needs clean up around shadow state tracking an
>    manipulation.
> 3. PPI state tracking needs to be heaviliy optimised to reduce the
>    number of locks taken and PPIs iterated over. This is now possible
>    with the introduction of the masks, but remains to be implemented.
> 4. Allow for sparse PPI state storage. Given that most of the 128
>    potential PPIs will never be used with a guest, it is extremely
>    wasteful to allocate storage for them.
> 
> These changes are based on v6.19-rc1. As before, the first commit has
> been cherry-picked from Marc's VTCR sanitisation series [3].
> 
> For those that are interested in the overall direction of the GICv5
> KVM support, Marc Zyngier has very kindly agreed to host the full
> *WIP* set of GICv5 KVM patches which can be found at [4]. These are
> not intended for review, and require some serious clean up, but
> should
> give a rough idea of what is still to come.
> 
> Thanks all for the feedback so far and any more you have,
> Sascha
> 
> [1] https://developer.arm.com/documentation/aes0070/latest
> [2]
> https://lore.kernel.org/all/20251212152215.675767-1-sascha.bischoff@arm.com/
> [3]
> https://lore.kernel.org/all/20251210173024.561160-1-maz@kernel.org/
> [4]
> https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=kvm-arm64/gicv5-full
> 

As an FYI, I've just posted the GICv5 kvmtool support for review here:

https://lore.kernel.org/all/20251219161240.1385034-1-sascha.bischoff@arm.com

Thanks,
Sascha