[PATCH v2 12/12] arm64: dts: qcom: hamoa: Add CoreSight nodes for APSS debug block
yuanfang Zhang
yuanfang.zhang at oss.qualcomm.com
Thu Dec 18 00:09:52 PST 2025
From: Jie Gan <jie.gan at oss.qualcomm.com>
The APSS debug block is built with CoreSight devices like ETM,
replicator, funnel and TMC ETF. Add dt nodes for these devices to enable
ETM trace.
Signed-off-by: Jie Gan <jie.gan at oss.qualcomm.com>
Co-developed-by: Yuanfang Zhang <yuanfang.zhang at oss.qualcomm.com>
Signed-off-by: Yuanfang Zhang <yuanfang.zhang at oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 926 ++++++++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/purwa.dtsi | 12 +
2 files changed, 938 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index a17900eacb20396a9792efcfcd6ce6dd877435d1..8c3de8bf058daa681db040c4a9a38253863e6c78 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -305,6 +305,210 @@ eud_in: endpoint {
};
};
+ etm-0 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&ncc0_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-1 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&ncc0_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-2 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&ncc0_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-3 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&ncc0_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-4 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&ncc1_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-5 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&ncc1_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-6 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&ncc1_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm-7 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&ncc1_3_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm8: etm-8 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu8>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm8_out: endpoint {
+ remote-endpoint = <&ncc2_0_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm9: etm-9 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu9>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm9_out: endpoint {
+ remote-endpoint = <&ncc2_1_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm10: etm-10 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu10>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm10_out: endpoint {
+ remote-endpoint = <&ncc2_2_rep_in>;
+ };
+ };
+ };
+ };
+
+ etm11: etm-11 {
+ compatible = "arm,coresight-etm4x-sysreg";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu11>;
+ qcom,skip-power-up;
+
+ out-ports {
+ port {
+ etm11_out: endpoint {
+ remote-endpoint = <&ncc2_3_rep_in>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-x1e80100", "qcom,scm";
@@ -6864,6 +7068,14 @@ funnel1_in2: endpoint {
};
};
+ port at 4 {
+ reg = <4>;
+
+ funnel1_in4: endpoint {
+ remote-endpoint = <&apss_funnel_out>;
+ };
+ };
+
port at 5 {
reg = <5>;
@@ -8154,6 +8366,720 @@ ddr_funnel1_out: endpoint {
};
};
+ apss_funnel: funnel at 12080000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x12080000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ apss_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_etf_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ apss_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_etf_out>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ apss_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint = <&funnel1_in4>;
+ };
+ };
+ };
+ };
+
+ funnel at 13401000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x13401000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 2 {
+ reg = <2>;
+
+ ncc0_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc at 13409000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x0 0x13409000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc0_etf_in: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator at 13490000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13490000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc0_0_rep_in: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_0_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator at 134a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x134a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc0_1_rep_in: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator at 134b0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x134b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc0_2_rep_in: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_2_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator at 134c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x134c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc0_3_rep_in: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_3_rep_out: endpoint {
+ remote-endpoint = <&ncc0_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel at 134d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x134d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd0>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ncc0_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc0_0_rep_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ncc0_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc0_1_rep_out>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ncc0_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc0_2_rep_out>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ncc0_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc0_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc0_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc0_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ funnel at 13901000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x13901000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 2 {
+ reg = <2>;
+
+ ncc1_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc at 13909000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x0 0x13909000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc1_etf_in: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator at 13990000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13990000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc1_0_rep_in: endpoint {
+ remote-endpoint = <&etm4_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_0_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ replicator at 139a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x139a0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc1_1_rep_in: endpoint {
+ remote-endpoint = <&etm5_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ replicator at 139b0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x139b0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc1_2_rep_in: endpoint {
+ remote-endpoint = <&etm6_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_2_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ replicator at 139c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x139c0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc1_3_rep_in: endpoint {
+ remote-endpoint = <&etm7_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_3_rep_out: endpoint {
+ remote-endpoint = <&ncc1_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel at 139d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x139d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd1>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ncc1_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc1_0_rep_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ncc1_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc1_1_rep_out>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ncc1_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc1_2_rep_out>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ncc1_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc1_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc1_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc1_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l2: funnel at 13e01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x13e01000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 2 {
+ reg = <2>;
+
+ ncc2_2_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_etf_in>;
+ };
+ };
+ };
+ };
+
+ cluster2_etf: tmc at 13e09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x0 0x13e09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc2_etf_in: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_etf_out: endpoint {
+ remote-endpoint = <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_0: replicator at 13e90000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13e90000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc2_0_rep_in: endpoint {
+ remote-endpoint = <&etm8_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_0_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_1: replicator at 13ea0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13ea0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc2_1_rep_in: endpoint {
+ remote-endpoint = <&etm9_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_2: replicator at 13eb0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13eb0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc2_2_rep_in: endpoint {
+ remote-endpoint = <&etm10_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_2_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ cluster2_rep_2_3: replicator at 13ec0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x0 0x13ec0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ port {
+ ncc2_3_rep_in: endpoint {
+ remote-endpoint = <&etm11_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_3_rep_out: endpoint {
+ remote-endpoint = <&ncc2_1_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ cluster2_funnel_l1: funnel at 13ed0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x0 0x13ed0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ power-domains = <&cluster_pd2>;
+ qcom,cpu-bound-components;
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ncc2_1_funnel_in0: endpoint {
+ remote-endpoint = <&ncc2_0_rep_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ncc2_1_funnel_in1: endpoint {
+ remote-endpoint = <&ncc2_1_rep_out>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ncc2_1_funnel_in2: endpoint {
+ remote-endpoint = <&ncc2_2_rep_out>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ncc2_1_funnel_in3: endpoint {
+ remote-endpoint = <&ncc2_3_rep_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ ncc2_1_funnel_out: endpoint {
+ remote-endpoint = <&ncc2_2_funnel_in2>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu at 15000000 {
compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi
index 2cecd2dd0de8c39f0702d6983bead2bc2adccf9b..38f2df9e42b60b5f22decfb464381bce214d414d 100644
--- a/arch/arm64/boot/dts/qcom/purwa.dtsi
+++ b/arch/arm64/boot/dts/qcom/purwa.dtsi
@@ -21,6 +21,18 @@
/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_zones;
+/delete-node/ &etm8;
+/delete-node/ &etm9;
+/delete-node/ &etm10;
+/delete-node/ &etm11;
+/delete-node/ &cluster2_funnel_l1;
+/delete-node/ &cluster2_funnel_l2;
+/delete-node/ &cluster2_etf;
+/delete-node/ &cluster2_rep_2_0;
+/delete-node/ &cluster2_rep_2_1;
+/delete-node/ &cluster2_rep_2_2;
+/delete-node/ &cluster2_rep_2_3;
+/delete-node/ &apss_funnel_in2;
&gcc {
compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
--
2.34.1
More information about the linux-arm-kernel
mailing list