[PATCH 29/32] irqchip/gic-v5: Check if impl is virt capable

[Sascha Bischoff]

On Tue, 2025-12-16 at 16:40 +0100, Lorenzo Pieralisi wrote:
> On Fri, Dec 12, 2025 at 03:22:45PM +0000, Sascha Bischoff wrote:
> > Now that there is support for creating a GICv5-based guest with
> > KVM,
> 
> The only comment I have is - as discussed, this patch is not really
> dependent on GICv5 KVM support - ie, if IRS_IDR0.VIRT == b0 there
> isn't
> a chance GIC v3 legacy support is implemented either, maybe it is
> worth
> clarifying that.

I've now explicitly called that out.

> Otherwise LGTM:
> 
> Reviewed-by: Lorenzo Pieralisi <lpieralisi at kernel.org>

Done, thanks!

Sascha

> 
> > check that the hardware itself supports virtualisation, skipping
> > the
> > setting of struct gic_kvm_info if not.
> > 
> > Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
> > ---
> >  drivers/irqchip/irq-gic-v5-irs.c   | 4 ++++
> >  drivers/irqchip/irq-gic-v5.c       | 5 +++++
> >  include/linux/irqchip/arm-gic-v5.h | 4 ++++
> >  3 files changed, 13 insertions(+)
> 
> 
> > 
> > diff --git a/drivers/irqchip/irq-gic-v5-irs.c
> > b/drivers/irqchip/irq-gic-v5-irs.c
> > index ce2732d649a3e..eebf9f219ac8c 100644
> > --- a/drivers/irqchip/irq-gic-v5-irs.c
> > +++ b/drivers/irqchip/irq-gic-v5-irs.c
> > @@ -744,6 +744,10 @@ static int __init gicv5_irs_init(struct
> > device_node *node)
> >  	 */
> >  	if (list_empty(&irs_nodes)) {
> >  
> > +		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);
> > +		gicv5_global_data.virt_capable =
> > +			!!FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
> > +
> >  		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
> >  		irs_setup_pri_bits(idr);
> >  
> > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-
> > gic-v5.c
> > index 41ef286c4d781..f5b17a2557aa1 100644
> > --- a/drivers/irqchip/irq-gic-v5.c
> > +++ b/drivers/irqchip/irq-gic-v5.c
> > @@ -1064,6 +1064,11 @@ static struct gic_kvm_info gic_v5_kvm_info
> > __initdata;
> >  
> >  static void __init gic_of_setup_kvm_info(struct device_node *node)
> >  {
> > +	if (!gicv5_global_data.virt_capable) {
> > +		pr_info("GIC implementation is not virtualization
> > capable\n");
> > +		return;
> > +	}
> > +
> >  	gic_v5_kvm_info.type = GIC_V5;
> >  
> >  	/* GIC Virtual CPU interface maintenance interrupt */
> > diff --git a/include/linux/irqchip/arm-gic-v5.h
> > b/include/linux/irqchip/arm-gic-v5.h
> > index 9607b36f021ee..36f4c0e8ef8e9 100644
> > --- a/include/linux/irqchip/arm-gic-v5.h
> > +++ b/include/linux/irqchip/arm-gic-v5.h
> > @@ -45,6 +45,7 @@
> >  /*
> >   * IRS registers and tables structures
> >   */
> > +#define GICV5_IRS_IDR0			0x0000
> >  #define GICV5_IRS_IDR1			0x0004
> >  #define GICV5_IRS_IDR2			0x0008
> >  #define GICV5_IRS_IDR5			0x0014
> > @@ -65,6 +66,8 @@
> >  #define GICV5_IRS_IST_STATUSR		0x0194
> >  #define GICV5_IRS_MAP_L2_ISTR		0x01c0
> >  
> > +#define GICV5_IRS_IDR0_VIRT		BIT(6)
> > +
> >  #define GICV5_IRS_IDR1_PRIORITY_BITS	GENMASK(22, 20)
> >  #define GICV5_IRS_IDR1_IAFFID_BITS	GENMASK(19, 16)
> >  
> > @@ -280,6 +283,7 @@ struct gicv5_chip_data {
> >  	u8			cpuif_pri_bits;
> >  	u8			cpuif_id_bits;
> >  	u8			irs_pri_bits;
> > +	bool			virt_capable;
> >  	struct {
> >  		__le64 *l1ist_addr;
> >  		u32 l2_size;
> > -- 
> > 2.34.1