[PATCH 19/32] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5

[Marc Zyngier]

On Fri, 12 Dec 2025 15:22:41 +0000,
Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:
> 
> Initialise the private interrupts (PPIs, only) for GICv5. This means
> that a GICv5-style intid is generated (which encodes the PPI type in
> the top bits) instead of the 0-based index that is used for older
> GICs.
> 
> Additionally, set all of the GICv5 PPIs to use Level for the handling
> mode, with the exception of the SW_PPI which uses Edge. This matches
> the architecturally-defined set in the GICv5 specification (the CTIIRQ
> handling mode is IMPDEF, so pick Level has been picked for that).
> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
> ---
>  arch/arm64/kvm/vgic/vgic-init.c    | 41 +++++++++++++++++++++++-------
>  include/linux/irqchip/arm-gic-v5.h |  2 ++
>  2 files changed, 34 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
> index b246cb6eae71b..51f4443cebcef 100644
> --- a/arch/arm64/kvm/vgic/vgic-init.c
> +++ b/arch/arm64/kvm/vgic/vgic-init.c
> @@ -263,13 +263,19 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type)
>  {
>  	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
>  	int i;
> +	u32 num_private_irqs;
> +
> +	if (vgic_is_v5(vcpu->kvm))
> +		num_private_irqs = VGIC_V5_NR_PRIVATE_IRQS;
> +	else
> +		num_private_irqs = VGIC_NR_PRIVATE_IRQS;

This is another case where we need to do something about
PPIs. Allocating the full complement of PPIs (all 128 of them) is
starting to be mildly visible (at 96 bytes a pop, that's 12kB of
storage per vcpu).

And 95% of that is guaranteed to be wasted... XArray anyone?

>  
>  	lockdep_assert_held(&vcpu->kvm->arch.config_lock);

It is good practice to leave this sort of assertions at the beginning
of the function.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.