[PATCH 1/2] perf mem: Simplify Arm SPE event config

[Ian Rogers]

On Fri, Dec 12, 2025 at 7:18 AM James Clark <james.clark at linaro.org> wrote:
>
> On 12/12/2025 14:44, Leo Yan wrote:
> > Since configuration fields default to zero, the zero assignments are
> > redundant, remove them.
> >
> > Signed-off-by: Leo Yan <leo.yan at arm.com>
> > ---
> >   tools/perf/arch/arm64/util/mem-events.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/tools/perf/arch/arm64/util/mem-events.c b/tools/perf/arch/arm64/util/mem-events.c
> > index 9f8da7937255cc9b14c3c58a1119b40bd0c76f6b..eaf00e0609c6c1b7d939a02fe3794471d1ed119b 100644
> > --- a/tools/perf/arch/arm64/util/mem-events.c
> > +++ b/tools/perf/arch/arm64/util/mem-events.c
> > @@ -6,7 +6,7 @@
> >   #define E(t, n, s, l, a) { .tag = t, .name = n, .event_name = s, .ldlat = l, .aux_event = a }
> >
> >   struct perf_mem_event perf_mem_events_arm[PERF_MEM_EVENTS__MAX] = {
> > -     E("spe-load",   "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/",      NULL,   true,   0),
> > -     E("spe-store",  "%s/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/",                     NULL,   false,  0),
> > +     E("spe-load",   "%s/ts_enable=1,pa_enable=1,load_filter=1,min_latency=%u/",     NULL,   true,   0),
> > +     E("spe-store",  "%s/ts_enable=1,pa_enable=1,store_filter=1/",                   NULL,   false,  0),
> >       E("spe-ldst",   "%s/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/",      NULL,   true,   0),
> >   };
> >
>
> Reviewed-by: James Clark <james.clark at linaro.org>

Reviewed-by: Ian Rogers <irogers at google.com>

Thanks,
Ian