[PATCH 09/32] KVM: arm64: gic-v5: Compute GICv5 FGTs on vcpu load

[Sascha Bischoff]

On Fri, 2025-12-12 at 16:24 +0000, Marc Zyngier wrote:
> On Fri, 12 Dec 2025 15:22:38 +0000,
> Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:
> > 
> > Extend the existing FGT infrastructure to calculate and activate
> > any
> > required GICv5 traps (ICH_HFGRTR_EL2, ICH_HFGWTR_EL2,
> > ICH_HFGITR_EL2)
> > before entering the guest, and restore the original ICH_HFGxTR_EL2
> > contents on the return path. This ensures that the host and guest
> > behaviour remains independent.
> > 
> > As of this change, none of the GICv5 instructions or register
> > accesses
> > are being trapped, but this will change in subsequent commits as
> > some
> > GICv5 system registers must always be trapped (ICC_IAFFIDR_EL1,
> > ICH_PPI_HMRx_EL1).
> 
> nit: 90% of this patch has nothing to do with computing the FGTs at
> load time. The gist of it is actually setting up the FGT
> infrastructure, and activate/deactivate aspect is actually very
> minor. You may want to reformulate the commit message to make that
> clearer (I don't think this needs splitting though).

Good point. Have reworded the commit message accordingly.

> 
> [...]
> 
> > @@ -1501,7 +1585,7 @@ static void __compute_hdfgwtr(struct kvm_vcpu
> > *vcpu)
> >  void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu)
> >  {
> >  	if (!cpus_have_final_cap(ARM64_HAS_FGT))
> > -		return;
> > +		goto skip_feat_fgt;
> 
> How can you have GICv5, but not FGTs? I don't think this is a valid
> construct as per the architecture:
> 
> 	(FEAT_GCIE ==> v9Ap3)
> 	(FEAT_FGT ==> v8Ap5)
> 	(v9Ap3 ==> (v9Ap2 && v8Ap8))

OK, agreed. FEAT_FGT is mandatory from v8.6. Have dropped this first
skip as we'll certainly have it if we have GICv5.

> 
> >  
> >  	__compute_fgt(vcpu, HFGRTR_EL2);
> >  	__compute_hfgwtr(vcpu);
> > @@ -1511,11 +1595,19 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu
> > *vcpu)
> >  	__compute_fgt(vcpu, HAFGRTR_EL2);
> >  
> >  	if (!cpus_have_final_cap(ARM64_HAS_FGT2))
> > -		return;
> > +		goto skip_feat_fgt;
> 
> Even FGT2 is expected, since v9.3 is congruent to v8.8:
> 
> 	(FEAT_FGT2 ==> v8Ap8)

FEAT_FGT2 is optional from v8.8 (v9.3), and mandatory from v8.9 (v9.4).
This means we could have a GICv5 system without FEAT_FGT2; I'll leave
in the second skip.

Thanks,
Sascha

> 
> >  
> >  	__compute_fgt(vcpu, HFGRTR2_EL2);
> >  	__compute_fgt(vcpu, HFGWTR2_EL2);
> >  	__compute_fgt(vcpu, HFGITR2_EL2);
> >  	__compute_fgt(vcpu, HDFGRTR2_EL2);
> >  	__compute_fgt(vcpu, HDFGWTR2_EL2);
> > +
> > +skip_feat_fgt:
> > +	if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
> > +		return;
> > +
> > +	__compute_fgt(vcpu, ICH_HFGRTR_EL2);
> > +	__compute_fgt(vcpu, ICH_HFGWTR_EL2);
> > +	__compute_fgt(vcpu, ICH_HFGITR_EL2);
> >  }
> 
> Thanks,
> 
> 	M.
>