[PATCH 31/32] Documentation: KVM: Introduce documentation for VGICv5

[Sascha Bischoff]

On Mon, 2025-12-15 at 09:56 +0000, Peter Maydell wrote:
> On Fri, 12 Dec 2025 at 15:24, Sascha Bischoff
> <Sascha.Bischoff at arm.com> wrote:
> > 
> > Now that it is possible to create a VGICv5 device, provide initial
> > documentation for it. At this stage, there is little to document.
> 
> Is userspace access to read/write the GICv5 register state also
> in the "will be added a in future patchseries" category ?
> 
> thanks
> -- PMM

Hi Peter,

That was the intent for now. Given that the order in which state is
read/written as part of, e.g., saving or restoring a guest matters
greatly, I am reluctant to post the userspace access patches piecemeal
(sys regs, IRS MMIO region, IRS SPI IST, IRS LPI IST, ITS MMIO region).
Also, this series is already rather lengthy, so I don't particularly
want to drag more things in.

FWIW, the current design for userspace access to the GICv5 system
registers looks precisely like what currently exists for GICv3 using
KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, and reuses this same ioctl.

Thanks,
Sascha