[PATCH 2/2] perf c2c: Update documentation for Arm SPE events

[James Clark]

On 12/12/2025 14:44, Leo Yan wrote:
> Document the default Arm SPE events used by the perf c2c tool.  Make a
> minor adjustment to the PowerPC entry for formatting consistency.
> 
> Suggested-by: Al Grant <al.grant at arm.com>
> Signed-off-by: Leo Yan <leo.yan at arm.com>
> ---
>   tools/perf/Documentation/perf-c2c.txt | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/perf/Documentation/perf-c2c.txt b/tools/perf/Documentation/perf-c2c.txt
> index 40b0f71a2c44eb642ff3bb234631a614b7c4fc9d..b765ae2511d2418a63092fb8a90a61faa335ac91 100644
> --- a/tools/perf/Documentation/perf-c2c.txt
> +++ b/tools/perf/Documentation/perf-c2c.txt
> @@ -170,11 +170,16 @@ following on AMD:
>   
>     ibs_op//
>   
> -and following on PowerPC:
> +following on PowerPC:
>   
>     cpu/mem-loads/
>     cpu/mem-stores/
>   
> +following on Arm:
> +
> +  arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,min_latency=30/
> +  arm_spe_0/ts_enable=1,pa_enable=1,store_filter=1/
> +

Technically there's 3 different ones on Arm because 
PERF_MEM_EVENTS__LOAD_STORE is also supported. Although I question the 
usefulness of these without labels or any text to say what the 
difference is, but that's an existing problem.

>   User can pass any 'perf record' option behind '--' mark, like (to enable
>   callchains and system wide monitoring):
>   
>