[PATCH v2] perf arm_spe: Add CPU variants supporting common data source packet

[James Clark]

On 13/11/2025 10:57 am, Leo Yan wrote:
> Add the following CPU variants to the list for data source decoding:
> 
>    - Cortex-A715 [1]
>    - Cortex-A78C [2]
>    - Cortex-X1 [3]
>    - Cortex-X4 [4]
>    - Neoverse V3 [5]
> 
> [1] https://developer.arm.com/documentation/101590/0103/Statistical-Profiling-Extension-Support/Statistical-Profiling-Extension-data-source-packet
> [2] https://developer.arm.com/documentation/102226/0002/Debug-descriptions/Statistical-Profiling-Extension/implementation-defined-features-of-SPE
> [3] https://developer.arm.com/documentation/101433/0102/Debug-descriptions/Statistical-Profiling-Extension/implementation-defined-features-of-SPE
> [4] https://developer.arm.com/documentation/102484/0003/Statistical-Profiling-Extension-support/Statistical-Profiling-Extension-data-source-packet
> [5] https://developer.arm.com/documentation/107734/0002/Statistical-Profiling-Extension-support/Statistical-Profiling-Extension-data-source-packet
> 
> Signed-off-by: Leo Yan <leo.yan at arm.com>
> ---
> Changes in v2:
> - Rebased on latest perf-tools-next branch.
> - Link to v1: https://lore.kernel.org/r/20251017-perf_arm_spe_update_midr_list-v1-1-9de407550354@arm.com
> ---
>   tools/perf/util/arm-spe.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
> index 614ce032f87e46d1f3754258f51bb1693ec128b7..f5bcc84eaa271f4dcc70bb585e517657e523de11 100644
> --- a/tools/perf/util/arm-spe.c
> +++ b/tools/perf/util/arm-spe.c
> @@ -570,16 +570,21 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,
>   }
>   
>   static const struct midr_range common_ds_encoding_cpus[] = {
> +	MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> +	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
> +	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
> +	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
>   	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
>   	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
>   	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
>   	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
>   	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
> +	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
>   	{},
>   };
>   
> 
> ---
> base-commit: da8fcfba0854dbe0b0eca465d35620c9cf4c89c1
> change-id: 20251017-perf_arm_spe_update_midr_list-b654cc2ac0dd
> 
> Best regards,

Reviewed-by: James Clark <james.clark at linaro.org>