[PATCH 4/4] dts: s32g: Add GPR syscon region
Dan Carpenter
dan.carpenter at linaro.org
Mon Dec 1 05:08:33 PST 2025
Add the GPR syscon region for the s32 chipset.
Signed-off-by: Dan Carpenter <dan.carpenter at linaro.org>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..3c9472f6c174 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon at 4007c000 {
+ compatible = "nxp,s32-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
ocotp: nvmem at 400a4000 {
compatible = "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -731,6 +738,7 @@ gmac0: ethernet at 4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index eff7673e7f34..0ceca3caf133 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon at 4007c000 {
+ compatible = "nxp,s32-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
ocotp: nvmem at 400a4000 {
compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -808,6 +815,7 @@ gmac0: ethernet at 4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.51.0
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