[PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver

[Krzysztof Kozlowski]

On 16/08/2025 12:47, Dan Carpenter wrote:
> Add the device tree information for the S32G On Chip One-Time
> Programmable Controller (OCOTP) chip.
> 
> Signed-off-by: Dan Carpenter <dan.carpenter at linaro.org>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
>  arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 09d2fbbe1d8c..e58ea0d3b083 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -612,5 +612,12 @@ gic: interrupt-controller at 50800000 {
>  			interrupt-controller;
>  			#interrupt-cells = <3>;
>  		};
> +
> +		ocotp: ocotp at 400a4000 {

Nodename: efuse@ or nvmem@

> +			compatible = "nxp,s32g2-ocotp";
> +			reg = <0x400a4000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};
>  	};
>  };
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 39effbe8217c..184a29dea184 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -681,6 +681,13 @@ gic: interrupt-controller at 50800000 {
>  			      <0x50420000 0x2000>;
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		ocotp: ocotp at 400a4000 {

Same here


Best regards,
Krzysztof