[PATCH] ARM: dts: renesas: Add boot phase tags marking to Renesas RZ/A1
Geert Uytterhoeven
geert at linux-m68k.org
Wed Aug 6 02:11:26 PDT 2025
Hi Marek,
On Mon, 30 Jun 2025 at 00:05, Marek Vasut
<marek.vasut+renesas at mailbox.org> wrote:
> bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
> to describe various node usage during boot phases with DT. Add bootph-all for
> all nodes that are used in the bootloader on Renesas RZ/A1 SoC.
>
> All SoC require BSC bus, PFC pin control and OSTM0 timer access during all
> stages of the boot process, those are marked using bootph-all property, and
> so is the SoC bus node which contains the PFC and OSTM IPs.
>
> Each board console UART is also marked as bootph-all to make it available in
> all stages of the boot process.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
Thanks for your patch!
> --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi
> @@ -41,6 +41,7 @@ bsc: bus {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0 0x18000000>;
> + bootph-all;
> };
>
> cpus {
> @@ -108,6 +109,8 @@ soc {
> #size-cells = <1>;
> ranges;
>
Please drop this blank line.
> + bootph-all;
> +
> L2: cache-controller at 3ffff000 {
> compatible = "arm,pl310-cache";
> reg = <0x3ffff000 0x1000>;
> @@ -639,6 +643,7 @@ ostm0: timer at fcfec000 {
> interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
> clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
> power-domains = <&cpg_clocks>;
> + bootph-all;
Please move this to the board-specific .dts files, where this node
is enabled.
> status = "disabled";
> };
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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