[PATCH v3 41/42] KVM: arm64: Add FGT descriptors for FEAT_FGT2

[Marc Zyngier]

On Tue, 29 Apr 2025 14:09:13 +0100,
Ben Horgan <ben.horgan at arm.com> wrote:
> 
> Hi Marc,
> 
> On 4/26/25 13:28, Marc Zyngier wrote:
> > Bulk addition of all the FGT2 traps reported with EC == 0x18,
> > as described in the 2025-03 JSON drop.
> > 
> > Signed-off-by: Marc Zyngier <maz at kernel.org>
> > ---
> >   arch/arm64/kvm/emulate-nested.c | 83 +++++++++++++++++++++++++++++++++
> >   1 file changed, 83 insertions(+)
> > 
> > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> > index 9c7ecfccbd6e9..f7678af272bbb 100644
> > --- a/arch/arm64/kvm/emulate-nested.c
> > +++ b/arch/arm64/kvm/emulate-nested.c
> [...]
> >   	/*
> >   	 * HDFGWTR_EL2
> >   	 *
> > @@ -1896,12 +1972,19 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
> >   	 * read-side mappings, and only the write-side mappings that
> >   	 * differ from the read side, and the trap handler will pick
> >   	 * the correct shadow register based on the access type.
> > +	 *
> > +	 * Same model applies to the FEAT_FGT2 registers.
> >   	 */
> >   	SR_FGT(SYS_TRFCR_EL1,		HDFGWTR, TRFCR_EL1, 1),
> >   	SR_FGT(SYS_TRCOSLAR,		HDFGWTR, TRCOSLAR, 1),
> >   	SR_FGT(SYS_PMCR_EL0,		HDFGWTR, PMCR_EL0, 1),
> >   	SR_FGT(SYS_PMSWINC_EL0,		HDFGWTR, PMSWINC_EL0, 1),
> >   	SR_FGT(SYS_OSLAR_EL1,		HDFGWTR, OSLAR_EL1, 1),
> > +
> > +	/* HDFGWTR_EL2 */
> A missing 2. HDFGWTR_EL2 should be HDFGWTR2_EL2.

All reported typos fixed, thanks you!

	M.

-- 
Without deviation from the norm, progress is not possible.