[PATCH 4/5] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board

[Yixun Lan]

Hi Andrew, Andre,

On 01:42 Thu 24 Apr     , Andre Przywara wrote:
> On Wed, 23 Apr 2025 18:58:37 +0200
> Andrew Lunn <andrew at lunn.ch> wrote:
> 
> Hi,
> 
> > > +&emac0 {
> > > +	phy-mode = "rgmii";  
> > 
> > Does the PCB have extra long clock lines in order to provide the
> > needed 2ns delay? I guess not, so this should be rgmii-id.
> 
> That's a good point, and it probably true.
> 
> > 
> > > +	phy-handle = <&ext_rgmii_phy>;
> > > +
> > > +	allwinner,tx-delay-ps = <300>;
> > > +	allwinner,rx-delay-ps = <400>;  
> > 
> > These are rather low delays, since the standard requires 2ns. Anyway,
> > once you change phy-mode, you probably don't need these.
> 
As I tested, drop these two properties making ethernet unable to work,
there might be some space to improve, but currently I'd leave it for now

> Those go on top of the main 2ns delay, I guess to accommodate some skew
> between the RX and TX lines, or to account for extra some PCB delay
> between clock and data? The vendor BSP kernels/DTs program those board
> specific values, so we have been following suit for a while, for the
> previous SoCs as well.
> I just tried, it also works with some variations of those values, but
> setting tx-delay to 0 stops communication.
> 
I'd not bother to try other combinations, and just stick to vendor's settings

thanks

-- 
Yixun Lan (dlan)