[PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock

[Geert Uytterhoeven]

Hi Marek,

On Sun, 13 Apr 2025 at 11:29, Marek Vasut <marek.vasut at mailbox.org> wrote:
> On 4/10/25 10:48 PM, Rob Herring wrote:
> > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote:
> >> Document 'aux' clock which are used to supply the PCIe bus. This
> >> is useful in case of a hardware setup, where the PCIe controller
> >> input clock and the PCIe bus clock are supplied from the same
> >> clock synthesiser, but from different differential clock outputs:
> >>
> >>   ____________                    _____________
> >> | R-Car PCIe |                  | PCIe device |
> >> |            |                  |             |
> >> |    PCIe RX<|==================|>PCIe TX     |
> >> |    PCIe TX<|==================|>PCIe RX     |
> >> |            |                  |             |
> >> |   PCIe CLK<|======..  ..======|>PCIe CLK    |
> >> '------------'      ||  ||      '-------------'
> >>                      ||  ||
> >>   ____________       ||  ||
> >> |  9FGV0441  |      ||  ||
> >> |            |      ||  ||
> >> |   CLK DIF0<|======''  ||
> >> |   CLK DIF1<|==========''
> >> |   CLK DIF2<|
> >> |   CLK DIF3<|
> >> '------------'
> >>
> >> The clock are named 'aux' because those are one of the clock listed in
> >> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which
> >> fit closest to the PCIe bus clock. According to that binding document,
> >> the 'aux' clock describe clock which supply the PMC domain, which is
> >> likely PCIe Mezzanine Card domain.
> >
> > Pretty sure that PMC is "power management controller" given it talks
> > about low power states.
> >
> >
> >>
> >> Tested-by: Niklas Söderlund <niklas.soderlund+renesas at ragnatech.se>
> >> Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
> >> ---
> >> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> >>        instead and add 'bus' clock outright ?
> >
> > Based on the diagram, this has nothing to do with the specific
> > controller. It should also probably a root port property, not host
> > bridge.
> How would you suggest I describe the clock which supply the PCIe bus
> clock lane (CLK DIF1 in the diagram) , which have to be enabled together
> with clock which supply the PCIe controller input clock lane (CLK DIF0) ?

I think Rob wants you to add clocks/clock-names for this to
dtschema/schemas/pci/pci-bus-common.yaml.  Then you can have pcie at M,N
subnode(s) with num-lanes, clock, and clock-names describing the PCIe
endpoint(s)?

git grep "pcie*@[0-9],[0-9]" -- $(git grep -l num-lanes -- Documentation/ )

Does that make sense?
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds