[PATCH v2] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE outputs for PCIe interfaces

[Siddharth Vadapalli]

On Sun, Apr 20, 2025 at 08:25:22AM +0530, Siddharth Vadapalli wrote:
> On Sat, Apr 19, 2025 at 06:38:00PM +0530, Kumar, Udit wrote:
> > Thanks for patch, Parth
> > 
> > On 4/4/2025 3:42 PM, Parth Pancholi wrote:
> 
> Hello Parth,
> 
> > > From: Parth Pancholi <parth.pancholi at toradex.com>
> > > 
> > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs
> > > from the SoC, which can be used to clock external PCIe endpoint devices.
> > > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock
> > > buffer, with each buffer supporting two PADs to provide reference clocks
> > > for two associated PCIe instances. The mappings are as follows:
> > >          - PCIe0 -> ACSPCIE1 PAD0
> > >          - PCIe1 -> ACSPCIE0 PAD0
> > >          - PCIe2 -> ACSPCIE1 PAD1
> > >          - PCIe3 -> ACSPCIE0 PAD1
> > > 
> > > This patch enables each ACSPCIE module and its corresponding PADs to ensure
> > > that all PCIE_REFCLK outputs are functional.
> > > 
> > > This change have been tested on an AM69-based custom hardware platform,
> > > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the
> > > internal PCIE_REFCLK are utilized with various endpoint devices such as
> > > a WiFi card, NVMe SSD, and PCIe-to-USB bridge.
> > 
> > You can enabling REFCLK to be out as default.
> > 
> > There are few boards, on which this clock is either terminated at test point
> > or not connected at all
> > 
> > Example AM69 board
> > 
> > PCIE_REFCLK2_P_OUT is not connected and PCIE_REFCLK0_P_OUT is terminated at
> > test points.
> > 
> > 
> > IMO, this clock to be enabled where this can be connected to PCIe EP.
> > 
> > Let Siddharth also share his comment, where to enable these clocks board
> > file or SOC file.
> 
> As Udit has pointed out, the reference clock outputs from ACSPCIE
> buffers should be enabled in the board files. I will be updating the
> patch that I had posted for enabling output of ACSPCIE0 PAD0 for PCIe1
> by moving the changes to the board file
> k3-j784s4-j742s2-evm-common.dtsi
> 
> Please update your patch accordingly. The overrides will no longer be
> required as the property will be defined in the board file itself for
> AM69.

I have posted the v3 series [0] which does the following:
1. Introduce the ACSPCIE0 node in the SoC file to allow reuse across:
   J784S4, J742S2 and AM69
2. Update 'pcie1_rc' node in the Board file specific to J784S4 and J742S2
   to drive the reference clock from PAD0 of ACSPCIE0

As a result, the current patch for AM69 can be converted to a series
which does the following:
1. Introduce the ACSPCIE1 node in the SoC file to allow reuse across:
   J784S4, J742S2 and AM69
2. Update 'pcie0_rc', 'pcie1_rc', 'pcie2_rc' and 'pcie3_rc' in the Board
   files to drive the reference clock from PAD0 and PAD1 of both
   ACSPCIE0 and ACSPCIE1

[0]: https://lore.kernel.org/r/20250422123218.3788223-1-s-vadapalli@ti.com/

Regards,
Siddharth.