[PATCH] perf arm-spe: Add support for SPE Data Source packet on HiSilicon HIP12
Yicong Yang
yangyicong at huawei.com
Tue Apr 22 03:11:34 PDT 2025
On 2025/4/22 17:16, James Clark wrote:
>
>
> On 08/04/2025 1:28 pm, Yicong Yang wrote:
>> From: Yicong Yang <yangyicong at hisilicon.com>
>>
>> Add data source encoding for HiSilicon HIP12 and coresponding mapping
>> to the perf's memory data source. This will help to synthesize the data
>> and support upper layer tools like perf-mem and perf-c2c.
>>
>> Signed-off-by: Yicong Yang <yangyicong at hisilicon.com>
>> ---
>> arch/arm64/include/asm/cputype.h | 2 +
>> tools/arch/arm64/include/asm/cputype.h | 2 +
>> .../util/arm-spe-decoder/arm-spe-decoder.h | 17 +++
>> tools/perf/util/arm-spe.c | 101 ++++++++++++++++++
>> 4 files changed, 122 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
>> index d1cc0571798b..36c5bbfbb6e9 100644
>> --- a/arch/arm64/include/asm/cputype.h
>> +++ b/arch/arm64/include/asm/cputype.h
>> @@ -133,6 +133,7 @@
>> #define HISI_CPU_PART_TSV110 0xD01
>> #define HISI_CPU_PART_HIP09 0xD02
>> +#define HISI_CPU_PART_HIP12 0xD06
>> #define APPLE_CPU_PART_M1_ICESTORM 0x022
>> #define APPLE_CPU_PART_M1_FIRESTORM 0x023
>> @@ -220,6 +221,7 @@
>> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
>> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
>> #define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
>> +#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)
>> #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
>> #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
>> #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
>> diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h
>> index 488f8e751349..9a5d85cfd1fb 100644
>> --- a/tools/arch/arm64/include/asm/cputype.h
>> +++ b/tools/arch/arm64/include/asm/cputype.h
>> @@ -129,6 +129,7 @@
>> #define FUJITSU_CPU_PART_A64FX 0x001
>> #define HISI_CPU_PART_TSV110 0xD01
>> +#define HISI_CPU_PART_HIP12 0xD06
>> #define APPLE_CPU_PART_M1_ICESTORM 0x022
>> #define APPLE_CPU_PART_M1_FIRESTORM 0x023
>> @@ -202,6 +203,7 @@
>> #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
>> #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
>> #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
>> +#define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12)
>> #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
>> #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
>> #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
>> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
>> index 5d232188643b..0410abed5009 100644
>> --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
>> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h
>> @@ -82,6 +82,23 @@ enum arm_spe_ampereone_data_source {
>> ARM_SPE_AMPEREONE_L2D = 0x9,
>> };
>> +enum arm_spe_hisi_hip_data_source {
>> + ARM_SPE_HISI_HIP_PEER_CPU = 0,
>> + ARM_SPE_HISI_HIP_PEER_CPU_HITM = 1,
>> + ARM_SPE_HISI_HIP_L3 = 2,
>> + ARM_SPE_HISI_HIP_L3_HITM = 3,
>> + ARM_SPE_HISI_HIP_PEER_CLUSTER = 4,
>> + ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM = 5,
>> + ARM_SPE_HISI_HIP_REMOTE_SOCKET = 6,
>> + ARM_SPE_HISI_HIP_REMOTE_SOCKET_HITM = 7,
>> + ARM_SPE_HISI_HIP_LOCAL = 8,
>> + ARM_SPE_HISI_HIP_REMOTE = 9,
>> + ARM_SPE_HISI_HIP_NC_DEV = 13,
>> + ARM_SPE_HISI_HIP_L2 = 16,
>> + ARM_SPE_HISI_HIP_L2_HITM = 17,
>> + ARM_SPE_HISI_HIP_L1 = 18,
>> +};
>> +
>> struct arm_spe_record {
>> enum arm_spe_sample_type type;
>> int err;
>> diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
>> index 2a9775649cc2..eceae4219601 100644
>> --- a/tools/perf/util/arm-spe.c
>> +++ b/tools/perf/util/arm-spe.c
>> @@ -571,6 +571,11 @@ static const struct midr_range ampereone_ds_encoding_cpus[] = {
>> {},
>> };
>> +static const struct midr_range hisi_hip_ds_encoding_cpus[] = {
>> + MIDR_ALL_VERSIONS(MIDR_HISI_HIP12),
>> + {},
>> +};
>> +
>> static void arm_spe__sample_flags(struct arm_spe_queue *speq)
>> {
>> const struct arm_spe_record *record = &speq->decoder->record;
>> @@ -718,9 +723,105 @@ static void arm_spe__synth_data_source_ampereone(const struct arm_spe_record *re
>> arm_spe__synth_data_source_common(&common_record, data_src);
>> }
>> +static void arm_spe__synth_data_source_hisi_hip(const struct arm_spe_record *record,
>> + union perf_mem_data_src *data_src)
>> +{
>> + /* Use common synthesis method to handle store operations */
>> + if (record->op & ARM_SPE_OP_ST) {
>> + arm_spe__synth_data_source_common(record, data_src);
>> + return;
>> + }
>> +
>> + switch (record->source) {
>> + case ARM_SPE_HISI_HIP_PEER_CPU:
>> + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>> + break;
>> + case ARM_SPE_HISI_HIP_PEER_CPU_HITM:
>> + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>> + break;
>> + case ARM_SPE_HISI_HIP_L3:
>> + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
>> + break;
>> + case ARM_SPE_HISI_HIP_L3_HITM:
>> + data_src->mem_lvl = PERF_MEM_LVL_L3 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>> + break;
>> + case ARM_SPE_HISI_HIP_PEER_CLUSTER:
>> + data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_NONE;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>> + break;
>> + case ARM_SPE_HISI_HIP_PEER_CLUSTER_HITM:
>> + data_src->mem_lvl = PERF_MEM_LVL_REM_CCE1 | PERF_MEM_LVL_HIT;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
>> + data_src->mem_snoop = PERF_MEM_SNOOP_HITM;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>> + break;
>> + case ARM_SPE_HISI_HIP_REMOTE_SOCKET:
>> + data_src->mem_lvl = PERF_MEM_LVL_REM_CCE2;
>> + data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
>> + data_src->mem_remote = PERF_MEM_REMOTE_REMOTE;
>> + data_src->mem_snoopx = PERF_MEM_SNOOPX_PEER;
>
> Hi Yicong,
>
> Is the mem_snoop setting missing from this one?
>
it should be PERF_MEM_SNOOP_NONE, will fix. Thanks for catching this.
> Other than that, LGTM.
>
Thanks.
More information about the linux-arm-kernel
mailing list