[PATCH 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1

[Siddharth Vadapalli]

On Sat, Apr 19, 2025 at 11:39:55PM +0530, Kumar, Udit wrote:

Hello Udit,

> 
> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
> > address space of the respective PCIe Controllers. Hence, update the
> > ranges to include them.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli at ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > index a7f2f52f42f7..4f5d277c97a4 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > @@ -126,6 +126,8 @@ cbass_main: bus at 100000 {
> >   			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
> >   			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
> >   			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
> > +			 <0x40 0x00000000 0x40 0x00000000 0x00 0x08000000>, /* PCIe0 DAT1 */
> > +			 <0x41 0x00000000 0x41 0x00000000 0x00 0x08000000>, /* PCIe1 DAT1 */
> 
> Do you want to map whole 4GB or just 128M ?

It should have been 4 GB and needs to be updated. Thank you for
reviewing the patch and pointing this out. I will fix this in the next
version of the series.

Regards,
Siddharth.