[PATCH] PCI: dw-rockchip: Configure max payload size on host init

[Niklas Cassel]

On Thu, Apr 17, 2025 at 05:48:04PM +0800, Hans Zhang wrote:
> 
> 
> On 2025/4/17 16:39, Niklas Cassel wrote:
> > On Thu, Apr 17, 2025 at 04:07:51PM +0800, Hans Zhang wrote:
> > > On 2025/4/17 15:48, Niklas Cassel wrote:
> > > 
> > > Hi Niklas and Shawn,
> > > 
> > > Thank you very much for your discussion and reply.
> > > 
> > > I tested it on RK3588 and our platform. By setting pci=pcie_bus_safe, the
> > > maximum MPS will be automatically matched in the end.
> > > 
> > > So is my patch no longer needed? For RK3588, does the customer have to
> > > configure CONFIG_PCIE_BUS_SAFE or pci=pcie_bus_safe?
> > > 
> > > Also, for pci-meson.c, can the meson_set_max_payload be deleted?
> > 
> > I think the only reason why this works is because
> > pcie_bus_configure_settings(), in the case of
> > pcie_bus_config == PCIE_BUS_SAFE, will walk the bus and set MPS in
> > the bridge to the lowest of the downstream devices:
> > https://github.com/torvalds/linux/blob/v6.15-rc2/drivers/pci/probe.c#L2994-L2999
> > 
> > 
> > So Hans, if you look at lspci for the other RCs/bridges that don't
> > have any downstream devices connected, do they also show DevCtl.MPS 256B
> > or do they still show 128B ?
> > 
> 
> Hi Niklas,
> 
> It will show DevCtl.MPS 256B.

Ok.

I guess that just means that the bridge itself is included in pci_walk_bus().

Let's wait and see what people think about my proposal earlier in the thread,
or if someone can think of something better.


Kind regards,
Niklas