[PATCH v2 08/15] arm64: dts: freescale: imx93-phyboard-segin: Fix SD-card pinctrl

[Frank Li]

On Tue, Apr 15, 2025 at 06:33:04AM +0200, Primoz Fiser wrote:
> Until now, all usdhc2 (SD-card) pinctrl labels pointed to one pinctrl
> group "usdhc2grp" which was overwritten twice by the 100 and 200 MHz
> modes. Fix this by using unique pinctrl names.
>
> Additionally, adjust MX93_PAD_SD2_CLK__USDHC2_CLK pad drive-strength
> according to values obtained by measurements from the PHYTEC hardware
> department to improve signal integrity.
>
> Signed-off-by: Primoz Fiser <primoz.fiser at norik.com>

Reviewed-by: Frank Li <Frank.Li at nxp.com>

Strange, DTC should report error if meet the same node name.

> ---
> Changes in v2:
> - reword commit msg
> - split errata changes into separate patch
>
>  arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> index 3d5cd0561362..541297052b62 100644
> --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
> @@ -77,7 +77,7 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00		0x31e
>
>  	pinctrl_usdhc2_default: usdhc2grp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK		0x179e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
>  			MX93_PAD_SD2_CMD__USDHC2_CMD		0x139e
>  			MX93_PAD_SD2_DATA0__USDHC2_DATA0	0x138e
>  			MX93_PAD_SD2_DATA1__USDHC2_DATA1	0x138e
> @@ -87,9 +87,9 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
>  		>;
>  	};
>
> -	pinctrl_usdhc2_100mhz: usdhc2grp {
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK            0x179e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x159e
>  			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
>  			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x138e
>  			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x138e
> @@ -99,9 +99,9 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
>  		>;
>  	};
>
> -	pinctrl_usdhc2_200mhz: usdhc2grp {
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
>  		fsl,pins = <
> -			MX93_PAD_SD2_CLK__USDHC2_CLK            0x178e
> +			MX93_PAD_SD2_CLK__USDHC2_CLK		0x158e
>  			MX93_PAD_SD2_CMD__USDHC2_CMD            0x139e
>  			MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x139e
>  			MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x139e
> --
> 2.34.1
>