[PATCH v2 1/2] arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1"

[Kumar, Udit]

On 4/8/2025 4:06 PM, Siddharth Vadapalli wrote:
> In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree
> nodes in the SoC file, enable them in the board file. The motivation for
> this change is that of following the existing convention of disabling
> nodes in the SoC file and only enabling the required ones in the board
> file.
>
> Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM")
> Cc: stable at vger.kernel.org
> Signed-off-by: Siddharth Vadapalli <s-vadapalli at ti.com>
> ---
>
> v1 of this patch is at:
> https://lore.kernel.org/r/20250408060636.3413856-2-s-vadapalli@ti.com/
> Changes since v1:
> - Added "Fixes" tag and updated commit message accordingly.
>
> Regards,
> Siddharth.
>
>   arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index 2127316f36a3..0bf2e1821662 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -843,6 +843,10 @@ &serdes_ln_ctrl {
>   		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
>   };
>   
> +&serdes_wiz0 {
> +	status = "okay";
> +};
> +
>   &serdes0 {
>   	status = "okay";
>   	serdes0_usb_link: phy at 0 {
> @@ -854,6 +858,10 @@ serdes0_usb_link: phy at 0 {
>   	};
>   };
>   
> +&serdes_wiz1 {
> +	status = "okay";
> +};
> +

Reviewed-by: Udit Kumar <u-kumar1 at ti.com>


>   &serdes1 {
>   	status = "okay";
>   	serdes1_pcie_link: phy at 0 {