[PATCH v5 2/9 RESEND] PCI: stm32: Add PCIe host support for STM32MP25
Manivannan Sadhasivam
manivannan.sadhasivam at linaro.org
Wed Apr 9 00:40:17 PDT 2025
On Tue, Mar 25, 2025 at 07:59:28AM +0100, Christian Bruel wrote:
> Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s
> controller based on the DesignWare PCIe core.
>
> Supports MSI via GICv2m, Single Virtual Channel, Single Function
>
> Supports WAKE# GPIO.
>
> Signed-off-by: Christian Bruel <christian.bruel at foss.st.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 12 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-stm32.c | 367 ++++++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-stm32.h | 15 +
> 4 files changed, 395 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c
> create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index b6d6778b0698..0c18879b604c 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -389,6 +389,18 @@ config PCIE_SPEAR13XX
> help
> Say Y here if you want PCIe support on SPEAr13XX SoCs.
>
> +config PCIE_STM32
PCIE_STM32_HOST since you are adding the PCIE_STM32_EP Kconfig.
> + tristate "STMicroelectronics STM32MP25 PCIe Controller (host mode)"
> + depends on ARCH_STM32 || COMPILE_TEST
> + depends on PCI_MSI
> + select PCIE_DW_HOST
> + help
> + Enables support for the DesignWare core based PCIe host controller
> + found in STM32MP25 SoC.
> +
> + This driver can also be built as a module. If so, the module
> + will be called pcie-stm32.
> +
> config PCI_DRA7XX
> tristate
>
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index a8308d9ea986..576d99cb3bc5 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> +obj-$(CONFIG_PCIE_STM32) += pcie-stm32.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-stm32.c b/drivers/pci/controller/dwc/pcie-stm32.c
> new file mode 100644
> index 000000000000..3937777d9eb9
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-stm32.c
> @@ -0,0 +1,367 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * STMicroelectronics STM32MP25 PCIe root complex driver.
> + *
> + * Copyright (C) 2025 STMicroelectronics
> + * Author: Christian Bruel <christian.bruel at foss.st.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_platform.h>
> +#include <linux/phy/phy.h>
> +#include <linux/pinctrl/devinfo.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/pm_wakeirq.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include "pcie-designware.h"
> +#include "pcie-stm32.h"
> +#include "../../pci.h"
> +
> +struct stm32_pcie {
> + struct dw_pcie pci;
> + struct regmap *regmap;
> + struct reset_control *rst;
> + struct phy *phy;
> + struct clk *clk;
> + struct gpio_desc *perst_gpio;
> + struct gpio_desc *wake_gpio;
> +};
> +
> +static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie)
> +{
You should add a delay of PCIE_T_PVPERL_MS to satisfy the PERST# deassertion
requirement as per the spec.
> + gpiod_set_value(stm32_pcie->perst_gpio, 0);
> +
> + if (stm32_pcie->perst_gpio)
> + msleep(PCIE_T_RRS_READY_MS);
> +}
> +
> +static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie)
> +{
> + gpiod_set_value(stm32_pcie->perst_gpio, 1);
> +}
> +
> +static int stm32_pcie_start_link(struct dw_pcie *pci)
> +{
> + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
> +
> + return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
> + STM32MP25_PCIECR_LTSSM_EN,
> + STM32MP25_PCIECR_LTSSM_EN);
> +}
> +
> +static void stm32_pcie_stop_link(struct dw_pcie *pci)
> +{
> + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
> +
> + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
> + STM32MP25_PCIECR_LTSSM_EN, 0);
> +}
> +
> +static int stm32_pcie_suspend_noirq(struct device *dev)
> +{
> + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = dw_pcie_suspend_noirq(&stm32_pcie->pci);
> + if (ret) {
> + stm32_pcie_deassert_perst(stm32_pcie);
> + return ret;
> + }
> +
> + stm32_pcie_assert_perst(stm32_pcie);
> +
> + clk_disable_unprepare(stm32_pcie->clk);
> +
> + if (!device_wakeup_path(dev))
> + phy_exit(stm32_pcie->phy);
> +
> + return pinctrl_pm_select_sleep_state(dev);
> +}
> +
> +static int stm32_pcie_resume_noirq(struct device *dev)
> +{
> + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev);
> + int ret;
> +
> + /*
> + * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK,
> + * thus if no device is present, must force it low with an init pinmux
> + * to be able to access the DBI registers.
> + */
> + if (!IS_ERR(dev->pins->init_state))
> + ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state);
> + else
> + ret = pinctrl_pm_select_default_state(dev);
> +
> + if (ret) {
> + dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret);
> + return ret;
> + }
> +
> + if (!device_wakeup_path(dev)) {
> + ret = phy_init(stm32_pcie->phy);
> + if (ret) {
> + pinctrl_pm_select_default_state(dev);
> + return ret;
> + }
> + }
> +
> + ret = clk_prepare_enable(stm32_pcie->clk);
> + if (ret)
> + goto err_phy_exit;
> +
> + stm32_pcie_deassert_perst(stm32_pcie);
> +
> + ret = dw_pcie_resume_noirq(&stm32_pcie->pci);
> + if (ret)
> + goto err_disable_clk;
> +
> + pinctrl_pm_select_default_state(dev);
> +
> + return 0;
> +
> +err_disable_clk:
> + stm32_pcie_assert_perst(stm32_pcie);
> + clk_disable_unprepare(stm32_pcie->clk);
> +
> +err_phy_exit:
> + phy_exit(stm32_pcie->phy);
> + pinctrl_pm_select_default_state(dev);
> +
> + return ret;
> +}
> +
> +static const struct dev_pm_ops stm32_pcie_pm_ops = {
> + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq,
> + stm32_pcie_resume_noirq)
> +};
> +
> +static const struct dw_pcie_host_ops stm32_pcie_host_ops = {
> +};
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> + .start_link = stm32_pcie_start_link,
> + .stop_link = stm32_pcie_stop_link
> +};
> +
> +static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie,
> + struct platform_device *pdev)
> +{
> + struct device *dev = stm32_pcie->pci.dev;
> + unsigned int wake_irq;
> + int ret;
> +
> + /* Start to enable resources with PERST# asserted from GPIO */
> +
'Start to enable resources with PERST# asserted'
> + ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE);
> + if (ret)
> + return ret;
> +
> + ret = phy_init(stm32_pcie->phy);
> + if (ret)
> + return ret;
> +
> + ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
> + STM32MP25_PCIECR_TYPE_MASK,
> + STM32MP25_PCIECR_RC);
> + if (ret)
> + goto err_phy_exit;
> +
> + stm32_pcie_deassert_perst(stm32_pcie);
> +
> + if (stm32_pcie->wake_gpio) {
> + wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio);
> + ret = dev_pm_set_dedicated_wake_irq(dev, wake_irq);
> + if (ret) {
> + dev_info(dev, "Failed to enable wake# %d\n", ret);
> + goto err_disable_clk;
err_assert_perst
Reset LGTM!
- Mani
--
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