sama5d27_wlsom1_ek : Maximum QSPI frequency

[Tudor Ambarus]

On 4/9/25 3:56 AM, Fabio Estevam wrote:
> Hi Tudor,

Hi, Fabio,

> 
> On a sama5d27_wlsom1_ek running 6.12 or today's linux-next the QSPI
> fails to probe:
> 
>  # dmesg | grep spi
>  spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff

It seems the read id operation fails.

>  # cat /proc/mtd
>  dev:    size   erasesize  name
>  #
> 
> If I revert your commit 417e58ea41ab ("ARM: dts: at91-sama5d27_wlsom1:
> Set sst26vf064b SPI NOR flash at its maximum frequency") then the
> probe succeeds:
> 
>  # dmesg | grep spi
>  6 fixed-partitions partitions found on MTD device spi0
>  Creating 6 MTD partitions on "spi0":
>  # cat /proc/mtd
>  dev:    size   erasesize  name
>  mtd0: 00040000 00001000 "at91bootstrap"
>  mtd1: 000c0000 00001000 "bootloader"
>  mtd2: 00040000 00001000 "bootloader env redundant"
>  mtd3: 00040000 00001000 "bootloader env"
>  mtd4: 00080000 00001000 "device tree"
>  mtd5: 00600000 00001000 "kernel"
> 
> In U-Boot, the maximum sama5d27_wlsom1_ek SPI clock is 50MHz.
> 
> at91-sama5d2_xplained is populated with an N25Q128A QSPI that can be
> clocked up to 104MHz. However, its dts limits it to 80MHz.
> 
> at91-ama5d29_curiosity is also populated with an SST26VF064B QSPI
> and also restrict the maximum SPI clock to 80MHz.
> 
> Any suggestions?
> 

It's been a while since I did that patch, it was brought to life from
downstream by Nicolas, but I trust myself I tested it. I don't have
access easily to the board, but I can give some hints:

1/ for the jedec,spi-nor compatible one shall set the maximum frequency
supported by the flash. Then the SPI controller will get that and use
the min(flash-max-speed, controller-max-speed). Be aware that even if
104MHz is passed to the controller, because of the atmel-qspi internal
clock divider, you may set in the SPI controller a speed smaller than that.

My assumption is that 80 MHz was chosen for other boards because it was
close to what the internal clock divider can output. Even so,
jedec,spi-nor shall specify its maximum supported frequency, it
shouldn't care about what the controller uses in the end.

U-boot and 50 MHz is a mistake. 50MHz is the read SFDP (serial flash
discoverable parameters) jesd216 standard requirement, so maybe the
spi-max-freq = 50 MHz comes from there. All the flashes that I've seen
up to now support read SFDP at their max supported frequency. So what
linux and u-boot SPI NOR does is to issue read SFDP command at the
flash's max frequency. It worked fine. Ideally we shall introduce per
operation frequency, but nobody worked on that.

2/ I'd check the statements that I made in the commit message.
Flash's datasheet says that:
• High-Speed Clock Frequency:
- 2.7V-3.6V: 104 MHz maximum
- 2.3V-3.6V: 80 MHz maximum

Is the flash operated at 3.3V on wlsom1 ek as I mentioned?
Does increasing/decreasing of spi-cs-setup-ns help?

I rely on Nicolas for further investigation. Or maybe he can add someone
in cc that can help.

Cheers,
ta