[PATCH 1/2] clk: rockchip: clk-pll: Fix CRU_xx_CON2 register usage

[Alexander Shiyan]

According to RK3588 TRM, CRU_(CPLL/GPLL/etc)_CON2 register
(rate-k value) does not use highword write enable mask.
Lets fix this.

Signed-off-by: Alexander Shiyan <eagle.alexander923 at gmail.com>
---
 drivers/clk/rockchip/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 2c2abb3b4210..77ba4d6e7b5f 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -959,7 +959,7 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 		       HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
 		       pll->reg_base + RK3399_PLLCON(1));
 
-	writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
+	writel_relaxed((rate->k & RK3588_PLLCON2_K_MASK) << RK3588_PLLCON2_K_SHIFT,
 		       pll->reg_base + RK3399_PLLCON(2));
 
 	/* set pll power up */
-- 
2.39.1