[PATCH 01/14] arm64/fpsimd: Avoid RES0 bits in the SME trap handler

[Mark Brown]

On Fri, Apr 04, 2025 at 06:44:22PM +0100, Mark Rutland wrote:

> For SME traps taken with ESR_ELx.EC == 0b011101, the specific reason for
> the trap is indicated by ESR_ELx.ISS.SMTC ("SME Trap Code"). This field
> occupies bits [2:0] of ESR_ELx.ISS, and as of ARM DDI 0487 L.a, bits
> [24:3] of ESR_ELx.ISS are RES0. ESR_ELx.ISS itself occupies bits [24:0]
> of ESR_ELx.

Reviewed-by: Mark Brown <broonie at kernel.org>
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