[PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready

[Manivannan Sadhasivam]

On Wed, Apr 02, 2025 at 07:59:26AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>
> > Sent: 2025年4月2日 15:08
> > To: Hongxing Zhu <hongxing.zhu at nxp.com>
> > Cc: Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de; lpieralisi at kernel.org;
> > kw at linux.com; robh at kernel.org; bhelgaas at google.com;
> > shawnguo at kernel.org; s.hauer at pengutronix.de; kernel at pengutronix.de;
> > festevam at gmail.com; linux-pci at vger.kernel.org;
> > linux-arm-kernel at lists.infradead.org; imx at lists.linux.dev;
> > linux-kernel at vger.kernel.org
> > Subject: Re: [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23
> > ready
> > 
> > On Fri, Mar 28, 2025 at 11:02:10AM +0800, Richard Zhu wrote:
> > > ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through
> > > Beacon or PERST# De-assertion
> > 
> > Is it possible to share the link to the erratum?
> > 
> Sorry, the erratum document isn't ready to be published yet.
> > >
> > > When the auxiliary power is not available, the controller cannot exit
> > > from
> > > L23 Ready with beacon or PERST# de-assertion when main power is not
> > > removed.
> > >
> > 
> > I don't understand how the presence of Vaux affects the controller. Same goes
> > for PERST# deassertion. How does that relate to Vaux? Is this erratum for a
> > specific endpoint behavior?
> IMHO I don't know the exact details of the power supplies in this IP design.
> Refer to my guess , maybe the beacon detect or wake-up logic in designs is
>  relied on the status of SYS_AUX_PWR_DET signals in this case.

Can you please try to get more details? I couldn't understand the errata.

- Mani

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