[PATCH v1 1/2] arm64: dts: mediatek: mt8195: Add subsys clks for PCIe power domains

[Chen-Yu Tsai]

On Wed, Apr 2, 2025 at 5:10 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno at collabora.com> wrote:
>
> The PCIe MAC needs the sram to be powered on for internal IP
> access and it has always worked before because the bootloader
> on Chromebooks was leaving the PCIe PERI_AO MEM clocks on
> before booting the kernel.
> Add the SRAM (mem) clock as a subsystem clock on the PCIe MAC
> P0 and P1 to correctly describe the hardware and to avoid any
> issue with bootloaders behaving differently.
>
> Fixes: 2b515194bf0c ("arm64: dts: mt8195: Add power domains controller")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b33726da900b..0cb96cba727a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -792,12 +792,16 @@ power-domain at MT8195_POWER_DOMAIN_CAM_MRAW {
>
>                                 power-domain at MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
>                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
> +                                       clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
> +                                       clock-names = "ss-pextp0-mem";

Doesn't the PCIe host controller already reference this clock?

>                                         mediatek,infracfg = <&infracfg_ao>;
>                                         #power-domain-cells = <0>;
>                                 };
>
>                                 power-domain at MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
>                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
> +                                       clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P1_MEM>;
> +                                       clock-names = "ss-pextp1-mem";

Not this one though, since:

         /* Designer has connect pcie1 with peri_mem_p0 clock */
         <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;


ChenYu

>                                         mediatek,infracfg = <&infracfg_ao>;
>                                         #power-domain-cells = <0>;
>                                 };
> --
> 2.48.1
>
>