[PATCH v2 net] net: stmmac: dwmac4: extend timeout for VLAN Tag register busy bit check
Shenwei Wang
shenwei.wang at nxp.com
Fri Sep 20 07:24:29 PDT 2024
> -----Original Message-----
> From: Andrew Lunn <andrew at lunn.ch>
> Sent: Wednesday, September 18, 2024 6:58 PM
> To: Shenwei Wang <shenwei.wang at nxp.com>
> Cc: David S. Miller <davem at davemloft.net>; Eric Dumazet
> <edumazet at google.com>; Jakub Kicinski <kuba at kernel.org>; Paolo Abeni
> <pabeni at redhat.com>; Maxime Coquelin <mcoquelin.stm32 at gmail.com>;
> horms at kernel.org; Alexandre Torgue <alexandre.torgue at foss.st.com>; Jose
> Abreu <joabreu at synopsys.com>; Ong Boon Leong <boon.leong.ong at intel.com>;
> Wong Vee Khee <vee.khee.wong at intel.com>; Chuah Kim Tatt
> <kim.tatt.chuah at intel.com>; netdev at vger.kernel.org; linux-stm32 at st-md-
> mailman.stormreply.com; linux-arm-kernel at lists.infradead.org;
> imx at lists.linux.dev; dl-linux-imx <linux-imx at nxp.com>
> Subject: [EXT] Re: [PATCH v2 net] net: stmmac: dwmac4: extend timeout for
> VLAN Tag register busy bit check
> > Overnight testing revealed that when EEE is active, the busy bit can
> > remain set for up to approximately 300ms. The new 500ms timeout
> > provides a safety margin.
>
> Do you know what EEE has to do with VLAN filtering?
>
The exact design details are not available to me, but my understanding is that the Busy Bit is synchronized to the RX clock
supplied by the PHY. When EEE is active and the PHY enters LPI state, the RX clock is gated, preventing updates to the Busy Bit.
The question is the significant delay observed, especially considering that the PHY transitions between active and LPI states
multiple times during this period. There should have a lot of chances to update the Busy Bit sooner when it is in the active state.
> Could there be other registers which suffer from the same problem?
>
So far I think it only impact the VLAN status register because those bits are driven by another clock instead of CSR clock.
Based on current observations, it appears that this issue primarily affects the VLAN status register. The reason for this
is that the bits in the VLAN status register are driven by a clock source distinct from the CSR clock.
Regards,
Shenwei
> Andrew
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