[PATCH v2 2/2] arm64: cpufeature: Pretend that Apple A10 family does not support 32-bit EL0

[Catalin Marinas]

On Mon, Sep 16, 2024 at 09:41:12PM +0800, Nick Chan wrote:
> On 9/9/2024 17:10, Nick Chan wrote:
> > The Apple A10 family consists of physical performance and efficiency
> > cores, and only one of them can be active at a given time depending on
> > the current p-state. However, only the performance cores can execute
> > 32-bit EL0. This results in logical cores that can only execute 32-bit
> > EL0 in high p-states.
> 
> Further research shows that the MPIDR_EL1 values between the two core
> types are different. And whether the two core type have any extra
> differences is anyone's guess right now. So far, nothing seems to break
> horribly without special workarounds for the MPIDR value (with cpufreq
> enabled downstream) as:
> 1. There are no KVM, GIC, ACPI, PSCI or cpuidle
> 2. All CPUs switch P-mode and E-mode together
> 
> However, all of this is broken enough that this piece of code should go
> into arch/arm64/kernel/cpu_errata.c, and also generate a
> TAINT_CPU_OUT_OF_SPEC for these cursed CPUs.

I wouldn't carry any additional logic in the kernel for such
configuration (long time ago Arm had something similar, the big.LITTLE
switcher, but the CPUs were fairly similar from a feature perspective).

> > Trying to support 32-bit EL0 on a CPU that can only execute it in certain
> > states is a bad idea. The A10 family only supports 16KB page size anyway
> > so many AArch32 executables won't run anyways. Pretend that it does not
> > support 32-bit EL0 at all.

CONFIG_COMPAT depends on ARM64_4K_PAGES || EXPERT. Do we really need
these patches in case one enables EXPERT and tries to run 32-bit
binaries that never ran on 16K pages before?

-- 
Catalin