[PATCH v6 2/4] PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed

[Johan Hovold]

On Wed, Sep 04, 2024 at 09:19:44PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Sep 04, 2024 at 11:30:08AM +0200, Johan Hovold wrote:
> > On Wed, Sep 04, 2024 at 12:41:58PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam at linaro.org>

> > > +	/*
> > > +	 * Even if the platform doesn't want to limit the maximum link speed,
> > > +	 * just cache the hardware default value so that the vendor drivers can
> > > +	 * use it to do any link specific configuration.
> > > +	 */
> > > +	if (pci->max_link_speed < 0) {
> > 
> > This should be 
> > 
> > 	if (pci->max_link_speed < 1) {
> > 
> 
> Well I was trying to catch the error value here because if neither driver nor
> platform limits the max link speed, this would have -EINVAL (returned by
> of_pci_get_max_link_speed()).

Indeed, I thought I'd traced it do be zero here, but I must have made a
mistake. The old code did check for 0 before calling this function,
though (e.g. in case max_link_speed was never initialised as intended).

> But logically it makes sense to use 'pci->max_link_speed < 1' since anything
> below value 1 is an invalid value.
> 
> Will change it.

Sounds good.

> > > @@ -1058,8 +1069,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > >  {
> > >  	u32 val;
> > >  
> > > -	if (pci->max_link_speed > 0)
> > > -		dw_pcie_link_set_max_speed(pci, pci->max_link_speed);
> > > +	dw_pcie_link_set_max_speed(pci);

Johan