[PATCH] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control

[Will Deacon]

On Thu, Oct 24, 2024 at 11:41:11AM -0500, Rob Herring wrote:
> On Thu, Oct 24, 2024 at 5:40 AM Will Deacon <will at kernel.org> wrote:
> > On Wed, Oct 02, 2024 at 01:43:24PM -0500, Rob Herring (Arm) wrote:
> > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
> > > index 0afe02f879b4..bb93d32b86ea 100644
> > > --- a/drivers/perf/arm_pmuv3.c
> > > +++ b/drivers/perf/arm_pmuv3.c
> > > @@ -770,18 +770,27 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
> > >       int i;
> > >       struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
> > >
> > > -     /* Clear any unused counters to avoid leaking their contents */
> > > -     for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask,
> > > -                         ARMPMU_MAX_HWEVENTS) {
> > > -             if (i == ARMV8_PMU_CYCLE_IDX)
> > > -                     write_pmccntr(0);
> > > -             else if (i == ARMV8_PMU_INSTR_IDX)
> > > -                     write_pmicntr(0);
> > > -             else
> > > -                     armv8pmu_write_evcntr(i, 0);
> > > +     if (is_pmuv3p9(cpu_pmu->pmuver)) {
> > > +             u64 mask = 0;
> > > +             for_each_set_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) {
> > > +                     if (armv8pmu_event_has_user_read(cpuc->events[i]))
> > > +                             mask |= BIT(i);
> > > +             }
> > > +             write_pmuacr(mask);
> >
> > Since this is a new register, should we be zeroing it as part of our
> > reset callback?
> 
> That should not be necessary since EL0 access is gated off in PMUSEREN
> in general and enabling this register additionally requires setting
> the UEN bit. That's only done right after this.

That bit is set unconditionally, but it looks like we always write pmuacr
for v3p9 parts so it should be ok. Thanks.

Will