[PATCH v4 0/4] PCI: ep: dwc/imx6: Add bus address support for PCI endpoint devices

[Frank Li]

On Fri, Oct 25, 2024 at 04:36:26PM -0500, Bjorn Helgaas wrote:
> On Fri, Oct 25, 2024 at 05:05:03PM -0400, Frank Li wrote:
> > On Fri, Oct 25, 2024 at 03:48:18PM -0500, Bjorn Helgaas wrote:
> > > On Thu, Oct 24, 2024 at 04:41:42PM -0400, Frank Li wrote:
> > > > Endpoint          Root complex
> > > >                              ┌───────┐        ┌─────────┐
> > > >                ┌─────┐       │ EP    │        │         │      ┌─────┐
> > > >                │     │       │ Ctrl  │        │         │      │ CPU │
> > > >                │ DDR │       │       │        │ ┌────┐  │      └──┬──┘
> > > >                │     │◄──────┼─ATU ◄─┼────────┼─┤BarN│◄─┼─────────┘
> > > >                │     │       │       │        │ └────┘  │ Outbound Transfer
> > > >                └─────┘       │       │        │         │
> > > >                              │       │        │         │
> > > >                              │       │        │         │
> > > >                              │       │        │         │ Inbound Transfer
> > > >                              │       │        │         │      ┌──▼──┐
> > > >               ┌───────┐      │       │        │ ┌───────┼─────►│DDR  │
> > > >               │       │ outbound Transfer*    │ │       │      └─────┘
> > > >    ┌─────┐    │ Bus   ┼─────►│ ATU  ─┬────────┼─┘       │
> > > >    │     │    │ Fabric│Bus   │       │ PCI Addr         │
> > > >    │ CPU ├───►│       │Addr  │       │ 0xA000_0000      │
> > > >    │     │CPU │       │0x8000_0000   │        │         │
> > > >    └─────┘Addr└───────┘      │       │        │         │
> > > >           0x7000_0000        └───────┘        └─────────┘
> > > >
> > > > Add `bus_addr_base` to configure the outbound window address for CPU write.
> > > > The BUS fabric generally passes the same address to the PCIe EP controller,
> > > > but some BUS fabrics convert the address before sending it to the PCIe EP
> > > > controller.
> > > >
> > > > Above diagram, CPU write data to outbound windows address 0x7000_0000,
> > > > Bus fabric convert it to 0x8000_0000. ATU should use BUS address
> > > > 0x8000_0000 as input address and convert to PCI address 0xA000_0000.
> > >
> > > The above doesn't match what's in patch 1/4, and I think the version
> > > in 1/4 is better, so I'll comment there.
> > >
> > > To avoid confusion, it might be better not to duplicate it in 0/4 and
> > > 1/4.
> >
> > Yes, cover letter don't come into git tree. This part is common and
> > important, It is not good just said ref to patch1 commit message.
> >
> > Add do you have addition comment about this and
> > https://lore.kernel.org/imx/20241015-pci_fixup_addr-v5-0-ced556c85270@nxp.com/T/#t
> >
> > The both are the pave the road to clean up pci_fixup_addr().
>
> I think it would be helpful to combine the "PCI: dwc: optimize RC host
> pci_fixup_addr()" series and the "bus_addr_base" parts of this series
> together into a single series because they are doing very similar
> things, and it's easier to review them together.
>
> And split the dt-bindings, PHY sub mode, and new endpoint support
> parts to their own series because they're not related to the address
> translation changes.

new endpoint support depend on patch 1. let me merge two thread together
to review easily.

Frank

>
> Bjorn