[PATCH 3/3] perf: arm_cspmu: nvidia: enable NVLINK-C2C port filtering

[Will Deacon]

On Tue, Oct 15, 2024 at 05:29:28PM +0000, Besar Wicaksono wrote:
> > > diff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c
> > b/drivers/perf/arm_cspmu/nvidia_cspmu.c
> > > index d1cd9975e71a..cd51177347e5 100644
> > > --- a/drivers/perf/arm_cspmu/nvidia_cspmu.c
> > > +++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c
> > > @@ -149,6 +149,7 @@ static struct attribute *pcie_pmu_format_attrs[] = {
> > >
> > >  static struct attribute *nvlink_c2c_pmu_format_attrs[] = {
> > >       ARM_CSPMU_FORMAT_EVENT_ATTR,
> > > +     ARM_CSPMU_FORMAT_ATTR(port, "config1:0-1"),
> > >       NULL,
> > >  };
> > >
> > > @@ -193,7 +194,7 @@ static u32 nv_cspmu_event_filter(const struct
> > perf_event *event)
> > >       const struct nv_cspmu_ctx *ctx =
> > >               to_nv_cspmu_ctx(to_arm_cspmu(event->pmu));
> > >
> > > -     if (ctx->filter_mask == 0)
> > > +     if (ctx->filter_mask == 0 || event->attr.config1 == 0)
> > >               return ctx->filter_default_val;
> > 
> > Isn't this a bit too broad? It looks like this filter function is used
> > beyond the C2C PMU (i.e. the PCIe PMU) and you're also checking the whole
> > of config1 rather than just the port field.
> > 
> 
> I think the other PMUs (PCIE and CNVLINK) that have similar filters will also benefit
> from this change, since a filter value of 0 on these PMUs are meaningless. Should I
> make the intention clearer by moving this particular change into a separate patch?

Yes. If you want to change the behaviour for other PMUs, then please be
explicit about that. In any case, I don't think you should check the whole
of config1.

Will