[PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
Mark Rutland
mark.rutland at arm.com
Tue Oct 22 09:10:34 PDT 2024
On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote:
> Fine grained trap control for MDSELR_EL1 register needs to be configured in
> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2
> is also present. This adds a new helper __init_el2_fgt2() initializing this
> new FEAT_FGT2 based fine grained registers.
>
> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and
> watchpoint exceptions when kernel enters at EL1, but EL2 is also present.
> This updates __init_el2_debug() as required for FEAT_Debugv8p9.
>
> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements.
[...]
> + For CPUs with FEAT_Debugv8p9 extension present:
> +
> + - If the kernel is entered at EL1 and EL2 is present:
> +
> + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1
> + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1
> +
> + - If EL3 is present:
> +
> + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need
MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably
check if there's anything else we haven't yet documented in MDCR_EL3.
[...]
> .Lskip_trace_\@:
> + mrs x1, id_aa64dfr0_el1
> + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4
> + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9
> + b.lt .Lskip_dbg_v8p9_\@
> +
> + mov x0, #MDCR_EL2_EBWE
> + orr x2, x2, x0
That can be:
orr x2, x2, #MDCR_EL2_EBWE
Mark.
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