[PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block

[Hongxing Zhu]

Hi Alexander:

> -----Original Message-----
> From: Alexander Stein <alexander.stein at ew.tq-group.com>
> Sent: 2024年10月15日 17:19
> To: robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org;
> abelvesa at kernel.org; Peng Fan <peng.fan at nxp.com>;
> mturquette at baylibre.com; sboyd at kernel.org; shawnguo at kernel.org;
> s.hauer at pengutronix.de; festevam at gmail.com; Hongxing Zhu
> <hongxing.zhu at nxp.com>
> Cc: Hongxing Zhu <hongxing.zhu at nxp.com>; devicetree at vger.kernel.org;
> linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> linux-clk at vger.kernel.org; imx at lists.linux.dev; kernel at pengutronix.de
> Subject: Re: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block
>
> Hi Richard,
>
> Am Dienstag, 15. Oktober 2024, 09:34:04 CEST schrieb Richard Zhu:
> > CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> > enable/disable.
> >
> > Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF
> > clock out gate.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> > Reviewed-by: Frank Li <Frank.Li at nxp.com>
> > Reviewed-by: Peng Fan <peng.fan at nxp.com>
> > ---
> >  drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > index 19a62da74be4..25974947ad0c 100644
> > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> > @@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data
> netcmix_dev_data = {
> >     .clk_reg_offset = 0,
> >  };
> >
> > +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] =
> {
> > +   [0] = {
> > +           .name = "hsio_blk_ctl_clk",
> > +           .parent_names = (const char *[]){ "hsio_pll", },
> > +           .num_parents = 1,
> > +           .reg = 0,
>
> According to RM the register LFAST_IO_REG has offset 0xc0. How does the DT
> node look like?
> If this is the HSIO block control I would have expected this to control the whole
> block.
>
Thanks for your comments.
i.MX95 HSIO_BLK_CTL is a mix of kinds of setting registers of HSIO modules.
For example, Wakeup control of USB, AXI master QoS of USB and PCIe, and so on.
Only LFAST_IO_REG(offset 0xc0) register is used as clock out control.
So, only this register is contained in the commit.

Best Regards
Richard Zhu
> Best regards,
> Alexander
>
> > +           .bit_idx = 6,
> > +           .bit_width = 1,
> > +           .type = CLK_GATE,
> > +           .flags = CLK_SET_RATE_PARENT,
> > +   }
> > +};
> > +
> > +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> > +   .num_clks = 1,
> > +   .clk_dev_data = hsio_blk_ctl_clk_dev_data,
> > +   .clk_reg_offset = 0,
> > +};
> > +
> >  static int imx95_bc_probe(struct platform_device *pdev)  {
> >     struct device *dev = &pdev->dev;
> > @@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[]
> = {
> >     { .compatible = "nxp,imx95-display-master-csr", },
> >     { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
> >     { .compatible = "nxp,imx95-display-csr", .data =
> > &dispmix_csr_dev_data },
> > +   { .compatible = "nxp,imx95-hsio-blk-ctl", .data =
> > +&hsio_blk_ctl_dev_data },
> >     { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
> >     { .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
> >     { /* Sentinel */ },
> >
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-g/
> roup.com%2F&data=05%7C02%7Chongxing.zhu%40nxp.com%7Cd6eebc10596
> 440beb9a008dcecfa6a25%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C638645807490320855%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAw
> MDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&s
> data=dwZ8j9yLIr0h1aO0qZYE9xjMrQVXsr1iboa4wDLwmss%3D&reserved=0
>