[v3 PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for 32-bit sid size

[Yang Shi]

On 10/7/24 10:50 AM, Jason Gunthorpe wrote:
> On Fri, Oct 04, 2024 at 06:53:25PM -0700, Yang Shi wrote:
>
>> Yes, SIZE_MAX is ~(size_t)0, but size_t is unsigned long on ARM64. So the
>> check actually doesn't do what I expect it should do. U32_MAX should be
>> used.
> SIZE_MAX is right:
>
> static inline void *dmam_alloc_coherent(struct device *dev, size_t size,
> 		dma_addr_t *dma_handle, gfp_t gfp)
>
> It is up to dmam_alloc_coherent() to not truncate it's arguments, when
> you pass the u64 bounded to SIZE_MAX you guarentee that size will be a
> valid value.

SIZE_MAX is fine for dmam_alloc_coherent(). The concern from Daniel is 
the later assignment to cfg->linear.num_ents may truncate the value, 
which is unsigned int.

If I read the code correctly, it looks like dmam_alloc_coherent() may 
not guarantee to fail large allocation, for example, a very large cma 
area is configured. It is ridiculous, but it is allowed. Please correct 
me if I'm wrong. So the concern seems valid to me, so I proposed U32_MAX.

>
>>> I think it should be capped to STRTAB_MAX_L1_ENTRIES
>> I'm not expert on SMMU. Does the linear stream table have the same cap as
>> 2-level stream table? Is this defined by the hardware spec? If it is not,
>> why should we pick this value?
> Well, the way the driver works is in the 2 level mode it caps the
> whole table to STRTAB_MAX_L1_ENTRIES * STRTAB_NUM_L2_STES total SIDs
> which is 0x2000000 or 26 bits
>
> I guess there is a reasonable argument that linear or 2 level should
> have the same software enforced max size. Though would put it at a max
> 2G linear STE which is still larger than Linux can allocate, so it
> doesn't really make any practical difference compared to SIZE_MAX.
>
> Jason