[v2 PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for 32-bit sid size
Jason Gunthorpe
jgg at ziepe.ca
Wed Oct 2 11:14:58 PDT 2024
On Wed, Oct 02, 2024 at 10:55:14AM -0700, Yang Shi wrote:
> Using 64 bit immediate when doing shift can solve the problem. The
> disassembly after the fix looks like:
> ldr w20, [x19, 828] //, smmu_7(D)->sid_bits
> mov x0, 1
> lsl x0, x0, x20
>
> There are a couple of problematic places, extracted the shift into a helper.
>
> [1] https://lore.kernel.org/lkml/d4b53bbb-333a-45b9-9eb0-23ddd0820a14@arm.com/
> Fixes: ce410410f1a7 ("iommu/arm-smmu-v3: Add arm_smmu_strtab_l1/2_idx()")
> Tested-by: James Morse <james.morse at arm.com>
> Signed-off-by: Yang Shi <yang at os.amperecomputing.com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++
> 2 files changed, 10 insertions(+), 3 deletions(-)
Reviewed-by: Jason Gunthorpe <jgg at nvidia.com>
Jason
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