[PATCH] KVM: arm64: Fix S1/S2 combination when FWB==1 and S2 has Device memory type

[Marc Zyngier]

On Tue, 26 Nov 2024 15:27:00 +0000,
Oliver Upton <oliver.upton at linux.dev> wrote:
> 
> On Mon, Nov 25, 2024 at 09:47:56AM +0000, Marc Zyngier wrote:
> > The G.a revision of the ARM ARM had it pretty clear that HCR_EL2.FWB
> > had no influence on "The way that stage 1 memory types and attributes
> > are combined with stage 2 Device type and attributes." (D5.5.5).
> > 
> > However, this wording was lost in further revisions of the architecture.
> > 
> > Restore the intended behaviour, which is to take the strongest memory
> > type of S1 and S2 in this case, as if FWB was 0. The specification is
> > being fixed accordingly.
> 
> Since you're already asking for a spec fix, could you mention that the
> column headers in DDI0487K.a Table D8-95 are incorrect? MemAttr[1:0] is
> used twice, although I believe the first column is actually MemAttr[3:2].

That one has already been fixed as D22366, as described in the Known
Issues document for version K.a (issue 07) [1].

Thanks,

	M.

[1] https://developer.arm.com/documentation/102105/latest/

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