[v10,3/3] drm/rockchip: Add basic RK3588 HDMI output support

[Guenter Roeck]

On Wed, Oct 16, 2024 at 11:06:53PM +0300, Cristian Ciocaltea wrote:
> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
> Samsung IP block.
> 
> Add just the basic support for now, i.e. RGB output up to 4K at 60Hz,
> without audio, CEC or any of the HDMI 2.1 specific features.
> 
> Co-developed-by: Algea Cao <algea.cao at rock-chips.com>
> Signed-off-by: Algea Cao <algea.cao at rock-chips.com>
> Tested-by: Heiko Stuebner <heiko at sntech.de>
> Reviewed-by: Maxime Ripard <mripard at kernel.org>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea at collabora.com>
> ---
[ ... ]

> +static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder)
> +{
> +	struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder);
> +	struct drm_crtc *crtc = encoder->crtc;
> +	unsigned long long rate;
> +
> +	/* Unconditionally switch to TMDS as FRL is not yet supported */
> +	gpiod_set_value(hdmi->enable_gpio, 1);
> +
> +	if (crtc && crtc->state) {
> +		rate = drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode,
> +						   8, HDMI_COLORSPACE_RGB);
> +		clk_set_rate(hdmi->ref_clk, rate);
> +		/*
> +		 * FIXME: Temporary workaround to pass pixel clock rate
> +		 * to the PHY driver until phy_configure_opts_hdmi
> +		 * becomes available in the PHY API. See also the related
> +		 * comment in rk_hdptx_phy_power_on() from
> +		 * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +		 */
> +		phy_set_bus_width(hdmi->phy, rate / 100);

On 32-bit systems:

ERROR: modpost: "__udivdi3" [drivers/gpu/drm/rockchip/rockchipdrm.ko] undefined!

in the mainline kernel.

If the driver is not build tested (much less working) on 32-bit builds,
please consider restricting it to 64 bit builds.

Thanks,
Guenter