[PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Tue, Nov 19, 2024 at 01:18:57PM +0000, Russell King (Oracle) wrote:
> On Tue, Nov 19, 2024 at 10:28:48AM +0000, Gupta, Suraj wrote:
> > > -----Original Message-----
> > > From: Russell King <linux at armlinux.org.uk>
> > > 
> > > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > > > On 11/18/24 10:56, Russell King (Oracle) wrote:
> > > > > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > > > >> Add AXI 2.5G MAC support, which is an incremental speed upgrade of
> > > > >> AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property is
> > > > >> used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> > > > >> If max-speed property is missing, 1G is assumed to support backward
> > > > >> compatibility.
> > > > >>
> > > > >> Co-developed-by: Harini Katakam <harini.katakam at amd.com>
> > > > >> Signed-off-by: Harini Katakam <harini.katakam at amd.com>
> > > > >> Signed-off-by: Suraj Gupta <suraj.gupta2 at amd.com>
> > > > >> ---
> > > > >
> > > > > ...
> > > > >
> > > > >> -  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > > MAC_ASYM_PAUSE |
> > > > >> -          MAC_10FD | MAC_100FD | MAC_1000FD;
> > > > >> +  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > > > >> + MAC_ASYM_PAUSE;
> > > > >> +
> > > > >> +  /* Set MAC capabilities based on MAC type */  if (lp->max_speed
> > > > >> + == SPEED_1000)
> > > > >> +          lp->phylink_config.mac_capabilities |= MAC_10FD |
> > > > >> + MAC_100FD | MAC_1000FD;  else
> > > > >> +          lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > > > >
> > > > > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> > > >
> > > > It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > > > (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > > 
> > > That means the patch is definitely wrong, and the proposed DT change is also
> > > wrong.
> > > 
> > > If it's a limitation of the PCS, that limitation should be applied via the PCS's
> > > .pcs_validate() method, not at the MAC level.
> > > 
> > As mentioned in IP PG (https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Ethernet-Overview#:~:text=Typical%20Ethernet%20Architecture-,MAC,-For%2010/100), it's limitation in MAC also.
> 
> I'm not reading it as a limitation of the MAC.
> 
> The limitation stated there is that internal mode (GMII) is only
> supported for 2.5Gbps speeds. At 2.5Gbps speeds, the clock rate is
> increased from 125MHz to 312.5MHz (which makes it non-compliant
> with 802.3-2008, because that version doesn't define 2.5Gbps speeds.)
> 
> So long as the clock rate and interface can be safely switched, I
> don't see any reason to restrict the MAC itself to be either
> 10/100/1G _or_ 2.5G.
> 
> Note that 2.5G will only become available if it is supported by one
> of the supported interface modes (e.g. 2500base-X). If the supported
> interface modes do not include a mode that supports >1G, then 2.5G
> won't be available even if MAC_2500FD is set in mac_capabilities.

Reading further, PG047 which is the PCS, suggests that it can operate
at 10, 100, 1G, and 2.5G.

Moreover, what I read there is that where a PCS core supports 2.5G, it
can operate at 10, 100, 1G or 2.5G depending on the clock. Note 2 in
"Transceiver ports".

However, it doesn't support TBI at 2.5Gbps mode, only the 2500BASE-X
PMA/PMD.

Also states "The core operates at 125 MHz for the 1 Gbps data rate
(1.25Gbps line rate) and 312.5 MHz at 2.5 Gbps data rates (3.125 Gbps
line rate) in modes having device transceivers." These differences in
clocking are typical for systems that support 1G and 2.5G.

So, I'm still wondering what the limitation is. If the MAC transmit
clock can only run at 125MHz, or only at 312.5MHz, depending on the
design, then yes, it would be appropriate to limit the MAC to 1G
(and below) or 2.5G speeds.

However, if there's designs that allow the transmit clock to be
configured at run time, then the system supports both speeds.

-- 
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