[PATCH v5 16/16] net: stmmac: platform: Fix PTP clock rate reading

[Jan Petrous via B4 Relay]

From: "Jan Petrous (OSS)" <jan.petrous at oss.nxp.com>

The stmmac driver supports many vendors SoCs using Synopsys-licensed
Ethernet controller IP. Most of these vendors reuse the stmmac_platform
codebase, which has a potential PTP clock initialization issue.
The PTP clock rate reading might require ungating what is not provided.

Fix the PTP clock initialization by enabling it immediately.

Signed-off-by: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index b1e4df1a86a0..db3e8ef4fc3a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -632,7 +632,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
 	clk_prepare_enable(plat->pclk);
 
 	/* Fall-back to main clock in case of no PTP ref is passed */
-	plat->clk_ptp_ref = devm_clk_get(&pdev->dev, "ptp_ref");
+	plat->clk_ptp_ref = devm_clk_get_enabled(&pdev->dev, "ptp_ref");
 	if (IS_ERR(plat->clk_ptp_ref)) {
 		plat->clk_ptp_rate = clk_get_rate(plat->stmmac_clk);
 		plat->clk_ptp_ref = NULL;

-- 
2.47.0