[PATCH v3 1/8] dt-bindings: clock: imx8m-clock: support spread spectrum clocking

[Krzysztof Kozlowski]

On 11/11/2024 12:57, Dario Binacchi wrote:
> 
> Thank you Peng, for the information.
> 
> Do you think it would make sense to add the PLL nodes with SSCG to the
> anatop node?
> 
> anatop: clock-controller at 30360000 {
>     compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
>     reg = <0x30360000 0x10000>;
>     #clock-cells = <1>;
> 
>     clk_video_pll1_ref_sel: clock-video-pll1-ref-sel at 28 {
>         compatible = "fsl,imx8mn-mux-clock";

No. Nodes per clock were long time ago NAKed.

>         #clock-cells = <0>;
>         clocks = <&osc_24m>, <&clk_dummy>, <&clk_dummy>, <&clk_dummy>;
>         fsl,anatop = <&anatop 0x28>;
>         fsl,bit-shift = <0>;
>         clock-output-names = "video_pll1_ref_sel";
>     };
> 
>     clk_video_pll1: clock-video-pll1 at 28 {
>         compatible = "fsl,pll14xx-clock";
>         #clock-cells = <0>;
>         clocks = <&clk_video_pll1_ref_sel>;
>         ...
>         fsl,ssc-modfreq-hz = <6000>;
>         fsl,ssc-modrate-percent = <3>;
>         fsl,ssc-modmethod = "down-spread";
>     };
> };
> 
> This example only considers the video PLL, so to be complete, it
> should also add the clk_audio_pll1,
> clk_audio_pll2 and clk_dram_pll nodes. It is based on an RFC series
> that I sent about a year ago,
> which was not accepted. In this way, the SSCG properties (i.e.,
> "fsl,ssc-modfreq-hz", "fsl,ssc-modrate-percent"
> and "fsl,ssc-modmethod") would be added to the relevant nodes, and I
> would take only the essential parts
> from that series. This would still mean implementing the PLL driver
> ("fsl,pll14xx-clock") and its mux ("fsl,imx8mn-mux-clock").
> 
> These clocks can then be added to the "clocks" list of the "ccm" node:
> 
> clk: clock-controller at 30380000 {
>     compatible = "fsl,imx8mn-ccm";
>     ...
>     clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
>                   <&clk_ext3>, <&clk_ext4>, <&clk_video_pll1>,
>                   <&clk_audio_pll1>, <&clk_audio_pll2>, <&clk_dram_pll>;
>     ...
> }
> 
These clocks can be added anyway.

Best regards,
Krzysztof