[PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Sean Anderson]

On 11/18/24 03:18, Suraj Gupta wrote:
> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> max-speed is made a required property, and it breaks DT ABI but driver
> implementation ensures backward compatibility and assumes 1G when this
> property is absent.
> Modify existing bindings description for 2.5G MAC.
> 
> Signed-off-by: Suraj Gupta <suraj.gupta2 at amd.com>
> ---
>  .../bindings/net/xlnx,axi-ethernet.yaml       | 44 +++++++++++++++++--
>  1 file changed, 40 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> index fb02e579463c..69e84e2e2b63 100644
> --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
>  description: |
>    Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
>    provides connectivity to an external ethernet PHY supporting different
> -  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
> +  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
>    segments of memory for buffering TX and RX, as well as the capability of
>    offloading TX/RX checksum calculation off the processor.
>  
> +  AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
> +
>    Management configuration is done through the AXI interface, while payload is
>    sent and received through means of an AXI DMA controller. This driver
>    includes the DMA driver code, so this driver is incompatible with AXI DMA
> @@ -62,6 +64,7 @@ properties:
>        - rgmii
>        - sgmii
>        - 1000base-x
> +      - 2500base-x
>  
>    xlnx,phy-type:
>      description:
> @@ -118,9 +121,9 @@ properties:
>      type: object
>  
>    pcs-handle:
> -    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
> -      modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
> -      and "phy-handle" should point to an external PHY if exists.
> +    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
> +      2500base-x modes, where "pcs-handle" should be used to point to the
> +      PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
>      maxItems: 1
>  
>    dmas:
> @@ -137,12 +140,17 @@ properties:
>      minItems: 2
>      maxItems: 32
>  
> +  max-speed:
> +    description:
> +      Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
> +

Can't you read this from the TEMAC ability register?

--Sean

>  required:
>    - compatible
>    - interrupts
>    - reg
>    - xlnx,rxmem
>    - phy-handle
> +  - max-speed
>  
>  allOf:
>    - $ref: /schemas/net/ethernet-controller.yaml#
> @@ -164,6 +172,7 @@ examples:
>          xlnx,rxmem = <0x800>;
>          xlnx,txcsum = <0x2>;
>          phy-handle = <&phy0>;
> +        max-speed = <1000>;
>  
>          mdio {
>              #address-cells = <1>;
> @@ -188,6 +197,7 @@ examples:
>          xlnx,txcsum = <0x2>;
>          phy-handle = <&phy1>;
>          axistream-connected = <&dma>;
> +        max-speed = <1000>;
>  
>          mdio {
>              #address-cells = <1>;
> @@ -198,3 +208,29 @@ examples:
>              };
>          };
>      };
> +
> +# AXI 2.5G MAC
> +  - |
> +    axi_ethernet_eth2: ethernet at a4000000 {
> +        compatible = "xlnx,axi-ethernet-1.00.a";
> +        interrupts = <0>;
> +        clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
> +        clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
> +        phy-mode = "2500base-x";
> +        reg = <0x40000000 0x40000>;
> +        xlnx,rxcsum = <0x2>;
> +        xlnx,rxmem = <0x800>;
> +        xlnx,txcsum = <0x2>;
> +        phy-handle = <&phy1>;
> +        axistream-connected = <&dma>;
> +        max-speed = <2500>;
> +
> +        mdio {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            phy2: ethernet-phy at 1 {
> +                device_type = "ethernet-phy";
> +                reg = <1>;
> +            };
> +        };
> +    };