[PATCH] clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate

[Marek Vasut]

On 11/15/24 6:09 PM, Luca Ceresoli wrote:
> Hi Marek,

Hi,

>> Commit 4fbb73416b10 ("arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1
>> frequency to 506.8 MHz") configures the Video PLL1 to a frequency from
>> which both your panel pixel clock and LDB serializer clock can be
>> successfully divided down.
>>
>> Which panel do you use ?
>>
>> Try this -- Revert this patch, check /sys/kernel/debug/clk/clk_summary
>> and compare it with (I assume) panel-simple.c entry for the panel you
>> use, and notice the disp_pix clock are likely a bit off. That's because
>> the lcdif driver did its best to divide those pixel clock down from
>> 1039500000 set in imx8mp.dtsi .
>>
>> If you really want accurate pixel clock for your panel, you need similar
>> change to 4fbb73416b10 and configure the Video PLL such that the
>> accurate pixel clock can be derived from it. The Video PLL cannot be set
>> to pixel clock, because the LDB serializer clock are either 7x the pixel
>> clock, or 3.5x the pixel clock (for dual link LVDS), so the Video PLL
>> has to be set to 7x or 3.5x pixel clock of the panel, then you should
>> get accurate pixel clock and a working panel again.
> 
> I found that I'm having the same issue that has been discussed in some
> related threads: the lcdif2 configures the video_pll1 to ~72 MHz, and
> later LDB tries to set it to 7x that value, failing.

Right, which is solved by configuring the Video PLL to the correct 
frequency in DT up front ... unless you have more than one output 
supplied by that Video PLL.

> I would have guessed your "[PATCH 1/2] clk: imx: clk-imx8mp: Allow LDB
> serializer clock reconfigure parent rate" would have fixed it, and it
> actually allwos the LDB to set a proper (7x) rate for video_pll1, but
> then also the media_disp2 goes to the same rate. Apparently the
> video_pll1 is not propagated to media_disp2. I haven't dug into this.
> 
> So this is not the bug I had suspected about video_pll1 rate
> computation.
> 
> For now my workaround is to set the exact rate to video_pll1 via
> assigned-clock-rates.
> 
> However this breaks the case of using both lcdif1 and lcdif2. For that
> I have added a reparenting of media_disp1 to sys_pll3 and it looks like
> working.

See the patch link in the previous email, if you can use one Audio PLL 
as PLL for the other DISP PIX, then you will be able to achieve accurate 
pixel clock on both outputs. Can you do that ?

> Would you mind keeping Miquèl and me in Cc in following discussions
> about the imx8mp video clocks? We are also facing this topic and we are
> happy to contribute.
Sure