[PATCH 1/2] drm/rockchip: dsi: Perform trivial code cleanups
Dragan Simic
dsimic at manjaro.org
Fri Nov 8 05:53:57 PST 2024
Perform a few trivial code cleanups, to make one logged message a bit more
consistent with the other logged messages by capitalizing its first word, and
to avoid line wrapping by using the 100-column width better.
No intended functional changes are introduced by these code cleanups.
Signed-off-by: Dragan Simic <dsimic at manjaro.org>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 58a44af0e9ad..f451e70efbdd 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -1379,7 +1379,7 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
}
if (!dsi->cdata) {
- DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
+ DRM_DEV_ERROR(dev, "No dsi-config for %s node\n", np->name);
return -EINVAL;
}
@@ -1408,19 +1408,16 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
dsi->pllref_clk = NULL;
} else {
ret = PTR_ERR(dsi->pllref_clk);
- DRM_DEV_ERROR(dev,
- "Unable to get pll reference clock: %d\n",
- ret);
+ DRM_DEV_ERROR(dev, "Unable to get pll reference clock: %d\n", ret);
return ret;
}
}
if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
if (IS_ERR(dsi->phy_cfg_clk)) {
ret = PTR_ERR(dsi->phy_cfg_clk);
- DRM_DEV_ERROR(dev,
- "Unable to get phy_cfg_clk: %d\n", ret);
+ DRM_DEV_ERROR(dev, "Unable to get phy_cfg_clk: %d\n", ret);
return ret;
}
}
@@ -1465,8 +1462,7 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
if (IS_ERR(dsi->dmd)) {
ret = PTR_ERR(dsi->dmd);
if (ret != -EPROBE_DEFER)
- DRM_DEV_ERROR(dev,
- "Failed to probe dw_mipi_dsi: %d\n", ret);
+ DRM_DEV_ERROR(dev, "Failed to probe dw_mipi_dsi: %d\n", ret);
return ret;
}
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