[PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts

[Melody Olvera]

On 11/2/2024 2:36 AM, Konrad Dybcio wrote:
> On 22.10.2024 1:21 AM, Melody Olvera wrote:
>> Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
>> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
>> reserved memory, interconnects, regulator, and SMMU nodes. Also add
>> MTP and QRD board dts files for sm8750.
>>
>> Co-developed-by: Taniya Das <quic_tdas at quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas at quicinc.com>
>> Co-developed-by: Jishnu Prakash <quic_jprakash at quicinc.com>
>> Signed-off-by: Jishnu Prakash <quic_jprakash at quicinc.com>
>> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh at quicinc.com>
>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh at quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera at quicinc.com>
>> ---
> [...]
>
>> +&spmi_bus {
>> +	pm8550ve_d: pmic at 3 {
> These usually go to a separate file each.. But I see why that would
> be difficult here.
>
> Lately I've been a fan of <socname>-pmics.dtsi. WDYT, Bjorn?

SGTM, if Bjorn is fine w it, I can make that change; I'll do it similar 
to x1e80100-pmics.dtsi.

>
> [...]
>
>> +		apps_smmu: iommu at 15000000 {
>> +			compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> +			reg = <0x0 0x15000000 0x0 0x100000>;
>> +
> [...]
>
>> +			#iommu-cells = <2>;
>> +			#global-interrupts = <1>;
> This is usually dma-coherent, you can determine that through a smoke
> test

Ah yes good catch; this is supposed to be dma-coherent. Will add.

>
>> +		};
>> +
>> +		intc: interrupt-controller at 16000000 {
>> +			compatible = "arm,gic-v3";
>> +			reg = <0x0 0x16000000 0x0 0x10000>,     /* GICD */
>> +			      <0x0 0x16080000 0x0 0x200000>;    /* GICR * 12 */
> These comments are copypasted gen to gen and don't bring much
> information atop what's in bindings
>

Ack. Will remove.

Thanks,
Melody