[PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m)

[Dmitry Baryshkov]

On Mon, Oct 14, 2024 at 04:55:19PM +0300, Dmitry Baryshkov wrote:
> Follow the ARM64 platform and implement simple cache information driver.
> As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is
> limited to the ARMv7 / ARMv7M, providing simple fallback or just
> returning -EOPNOTSUPP in case of older platforms.
> 
> In theory we should be able to skip CLIDR reading and assume that Dcache
> and Icache (or unified L1 cache) always exist if CTR is supported and
> returns sensible value. However I think this better be handled by the
> maintainers of corresponding platforms.
> 
> Other than just providing information to the userspace, this patchset is
> required in order to implement L2 cache driver (and in the end CPU
> frequency scaling) on ARMv7-based Qualcomm devices.

Sudeep, Ard, Arnd, Russell, I have been struggling to get reviews for
this for several months. Is there a chance to hear anything? I'd really
like to scratch this off my 'pending' list.

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> Changes in v2:
> - Handle cores like ARM1176, which have cpu_architecture() ==
>   CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR
>   register (because they are ARMv6) (Arnd).
> - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org

-- 
With best wishes
Dmitry