[PATCH 3/3] dt-bindings: display: vop2: Add VP clock resets

[Heiko Stübner]

Am Mittwoch, 15. Mai 2024, 18:19:29 CEST schrieb Conor Dooley:
> On Tue, May 14, 2024 at 11:19:47AM -0400, Detlev Casanova wrote:
> > Add the documentation for VOP2 video ports reset clocks.
> > One reset can be set per video port.
> > 
> > Signed-off-by: Detlev Casanova <detlev.casanova at collabora.com>
> 
> Are these resets valid for all VOPs or just the one on 3588?

Not in that form.
I.e. rk3588 has 4 video-ports (0-3), while rk3568 has 3 (0-2).

So the binding should take into account that rk3568 also has the
SRST_VOP0 ... SRST_VOP2.


Also, I guess we might not want to limit ourself to stuff we use?
I.e. the new VOP-design is one block with multiple video-ports

So for rk3568 I see
#define SRST_A_VOP
#define SRST_H_VOP
#define SRST_VOP0
#define SRST_VOP1
#define SRST_VOP2

similarly rk3588 has

#define SRST_H_VOP
#define SRST_A_VOP
#define SRST_D_VOP0
#define SRST_D_VOP1
#define SRST_D_VOP2
#define SRST_D_VOP3

as generalized reset lines.





> 
> > ---
> >  .../display/rockchip/rockchip-vop2.yaml       | 27 +++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> > index 2531726af306b..941fd059498d4 100644
> > --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> > @@ -65,6 +65,22 @@ properties:
> >        - const: dclk_vp3
> >        - const: pclk_vop
> >  
> > +  resets:
> > +    minItems: 3
> > +    items:
> > +      - description: Pixel clock reset for video port 0.
> > +      - description: Pixel clock reset for video port 1.
> > +      - description: Pixel clock reset for video port 2.
> > +      - description: Pixel clock reset for video port 3.
> > +
> > +  reset-names:
> > +    minItems: 3
> > +    items:
> > +      - const: dclk_vp0
> > +      - const: dclk_vp1
> > +      - const: dclk_vp2
> > +      - const: dclk_vp3
> > +
> >    rockchip,grf:
> >      $ref: /schemas/types.yaml#/definitions/phandle
> >      description:
> > @@ -128,6 +144,11 @@ allOf:
> >          clock-names:
> >            minItems: 7
> >  
> > +        resets:
> > +          minItems: 4
> > +        reset-names:
> > +          minItems: 4
> > +
> >          ports:
> >            required:
> >              - port at 0
> > @@ -183,6 +204,12 @@ examples:
> >                                "dclk_vp0",
> >                                "dclk_vp1",
> >                                "dclk_vp2";
> > +                resets = <&cru SRST_VOP0>,
> > +                         <&cru SRST_VOP1>,
> > +                         <&cru SRST_VOP2>;
> > +                reset-names = "dclk_vp0",
> > +                              "dclk_vp1",
> > +                              "dclk_vp2";
> >                  power-domains = <&power RK3568_PD_VO>;
> >                  iommus = <&vop_mmu>;
> >                  vop_out: ports {
>