[PATCH v3 4/4] ARM: Implement PAN for LPAE by TTBR0 page table walks disablement

[Florian Fainelli]

On 5/14/24 13:33, Linus Walleij wrote:
> On Tue, May 14, 2024 at 8:26 PM Florian Fainelli <f.fainelli at gmail.com> wrote:
>> On 5/14/24 10:03, Russell King (Oracle) wrote:
> 
>>> I would imagine that the problem is cpu_set_ttbcr(). Please try adding
>>> a "memory" clobber to the asm() instruction in there.
>>>
>>
>> I can confirm that with CONFIG_CC_OPTIMIZE_FOR_SIZE=y and the hunk below:
>>
>> diff --git a/arch/arm/include/asm/proc-fns.h
>> b/arch/arm/include/asm/proc-fns.h
>> index 9b3105a2a5e0..1087bd2af433 100644
>> --- a/arch/arm/include/asm/proc-fns.h
>> +++ b/arch/arm/include/asm/proc-fns.h
>> @@ -187,7 +187,7 @@ static inline unsigned int cpu_get_ttbcr(void)
>>
>>    static inline void cpu_set_ttbcr(unsigned int ttbcr)
>>    {
>> -       asm("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
>> +       asm("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr) : "memory");
>>    }
>>
>>    #else  /*!CONFIG_MMU */
>>
>> my Raspberry Pi 4B in AArch32 mode boots and runs user-space properly.
>>
>> Thanks a lot Russell!
> 
> Second that, very nicely pinpointed Russell!
> 
> Florian, do you want to send a patch or should I?

I was wondering if Russell was able to fold this directly into patch #2 
where cpu_set_ttbr() is added, so as to not break functionality across 
bisection.
-- 
Florian