[PATCH v6 3/3] pinctrl: imx: support SCMI pinctrl protocol for i.MX95
Peng Fan (OSS)
peng.fan at oss.nxp.com
Mon May 13 04:45:26 PDT 2024
From: Peng Fan <peng.fan at nxp.com>
The generic pinctrl-scmi.c driver could not be used for i.MX95 because
i.MX95 SCMI firmware not supports functions, groups or generic
'Pin Configuration Type and Enumerations' listed in SCMI Specification.
i.MX95 System Control Management Interface(SCMI) firmware only supports
below pin configuration types which are OEM specific types:
192: PIN MUX
193: PIN CONF
194: DAISY ID
195: DAISY VAL
To support Linux generic pinctrl properties(pinmux, bias-pull-[up,
down], and etc), need extract the value from the property and map
them to the format that i.MX95 SCMI pinctrl protocol understands,
so add this driver.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
drivers/pinctrl/freescale/Kconfig | 9 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx-scmi.c | 579 +++++++++++++++++++++++++++
3 files changed, 589 insertions(+)
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 27bdc548f3a7..711a5ab3ceb1 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -7,6 +7,15 @@ config PINCTRL_IMX
select PINCONF
select REGMAP
+config PINCTRL_IMX_SCMI
+ tristate "i.MX95 pinctrl driver using SCMI protocol interface"
+ depends on ARM_SCMI_PROTOCOL && OF || COMPILE_TEST
+ select PINMUX
+ select GENERIC_PINCONF
+ help
+ i.MX95 SCMI firmware provides pinctrl protocol. This driver
+ utilizes the SCMI interface to do pinctrl configuration.
+
config PINCTRL_IMX_SCU
tristate
depends on IMX_SCU
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 647dff060477..e79b4b06e71b 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -2,6 +2,7 @@
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
+obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c
new file mode 100644
index 000000000000..e5ecde1ed4e9
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Control and Power Interface (SCMI) Protocol based i.MX pinctrl driver
+ *
+ * Copyright 2024 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/scmi_protocol.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../pinctrl-utils.h"
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+#define DRV_NAME "scmi-pinctrl-imx"
+
+#define SCMI_NUM_CONFIGS 4
+
+struct scmi_pinctrl_imx {
+ struct device *dev;
+ struct scmi_protocol_handle *ph;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc pctl_desc;
+ struct pinfunction *functions;
+ unsigned int nfunctions;
+ struct pinctrl_pin_desc *pins;
+ unsigned int nr_pins;
+ const struct scmi_pinctrl_proto_ops *ops;
+ unsigned int grp_index;
+ struct pingroup *groups;
+ unsigned int ngroups;
+};
+
+/* SCMI pin control types, aligned with SCMI firmware */
+#define IMX_SCMI_NUM_CFG 4
+#define IMX_SCMI_PIN_MUX 192
+#define IMX_SCMI_PIN_CONFIG 193
+#define IMX_SCMI_PIN_DAISY_ID 194
+#define IMX_SCMI_PIN_DAISY_CFG 195
+
+/*
+ * pinmux format:
+ * pin[31:21]|mux[20:16]|daisy_value[15:12]|daisy_valid[11:11]|daisy_id[10:0]
+ */
+#define IMX_PIN_ID_MASK GENMASK(31, 21)
+#define IMX_PIN_MUX_MASK GENMASK(20, 16)
+#define IMX_PIN_DAISY_VAL_MASK GENMASK(15, 12)
+#define IMX_PIN_DAISY_VALID BIT(11)
+#define IMX_PIN_DAISY_ID_MASK GENMASK(10, 0)
+
+static inline u32 get_pin_no(u32 pinmux)
+{
+ return FIELD_GET(IMX_PIN_ID_MASK, pinmux);
+}
+
+static inline u32 get_pin_func(u32 pinmux)
+{
+ return FIELD_GET(IMX_PIN_MUX_MASK, pinmux);
+}
+
+static inline u32 get_pin_daisy_valid(u32 pinmux)
+{
+ return FIELD_GET(IMX_PIN_DAISY_VALID, pinmux);
+}
+
+static inline u32 get_pin_daisy_val(u32 pinmux)
+{
+ return FIELD_GET(IMX_PIN_DAISY_VAL_MASK, pinmux);
+}
+
+static inline u32 get_pin_daisy_no(u32 pinmux)
+{
+ return FIELD_GET(IMX_PIN_DAISY_ID_MASK, pinmux);
+}
+
+static int pinctrl_scmi_imx_map_pinconf_type(enum pin_config_param param,
+ u32 *mask, u32 *shift)
+{
+ u32 arg = param;
+
+ switch (arg) {
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ *mask = BIT(12);
+ *shift = 12;
+ break;
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ *mask = BIT(11);
+ *shift = 11;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ *mask = BIT(10);
+ *shift = 10;
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ *mask = BIT(9);
+ *shift = 9;
+ break;
+ case PIN_CONFIG_SLEW_RATE:
+ *mask = GENMASK(8, 7);
+ *shift = 7;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ *mask = GENMASK(6, 1);
+ *shift = 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int pinctrl_scmi_imx_dt_group_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *reserved_maps,
+ unsigned int *num_maps,
+ const char *func_name)
+{
+ struct device *dev = pctldev->dev;
+ unsigned long *cfgs = NULL;
+ unsigned int n_cfgs, reserve = 1;
+ int i, n_pins, ret;
+ u32 ncfg, val, mask, shift, pin_conf, pinmux_group;
+ unsigned long cfg[IMX_SCMI_NUM_CFG];
+ enum pin_config_param param;
+ struct property *prop;
+ const __be32 *p;
+
+ n_pins = of_property_count_u32_elems(np, "pinmux");
+ if (n_pins < 0) {
+ dev_warn(dev, "Can't find 'pinmux' property in node %pOFn\n", np);
+ return -EINVAL;
+ } else if (!n_pins) {
+ return -EINVAL;
+ }
+
+ ret = pinconf_generic_parse_dt_config(np, pctldev, &cfgs, &n_cfgs);
+ if (ret) {
+ dev_err(dev, "%pOF: could not parse node property\n", np);
+ return ret;
+ }
+
+ pin_conf = 0;
+ for (i = 0; i < n_cfgs; i++) {
+ param = pinconf_to_config_param(cfgs[i]);
+ ret = pinctrl_scmi_imx_map_pinconf_type(param, &mask, &shift);
+ if (ret) {
+ dev_err(dev, "Error map pinconf_type %d\n", ret);
+ goto free_cfgs;
+ }
+
+ val = pinconf_to_config_argument(cfgs[i]);
+
+ pin_conf |= (val << shift) & mask;
+
+ }
+
+ reserve = n_pins * (1 + n_cfgs);
+
+ ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
+ reserve);
+ if (ret < 0)
+ goto free_cfgs;
+
+ of_property_for_each_u32(np, "pinmux", prop, p, pinmux_group) {
+ u32 pin_id, pin_func, daisy_id, daisy_val, daisy_valid;
+ const char *pin_name;
+
+ i = 0;
+ ncfg = IMX_SCMI_NUM_CFG;
+ pin_id = get_pin_no(pinmux_group);
+ pin_func = get_pin_func(pinmux_group);
+ daisy_id = get_pin_daisy_no(pinmux_group);
+ daisy_val = get_pin_daisy_val(pinmux_group);
+ cfg[i++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, pin_func);
+ cfg[i++] = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, pin_conf);
+
+ daisy_valid = get_pin_daisy_valid(pinmux_group);
+ if (daisy_valid) {
+ cfg[i++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_ID,
+ daisy_id);
+ cfg[i++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG,
+ daisy_val);
+ } else {
+ ncfg -= 2;
+ }
+
+ pin_name = pin_get_name(pctldev, pin_id);
+
+ dev_dbg(dev, "pin: %s, pin_conf: 0x%x, daisy_id: %u, daisy_val: 0x%x\n",
+ pin_name, pin_conf, daisy_id, daisy_val);
+
+ ret = pinctrl_utils_add_map_configs(pctldev, map, reserved_maps,
+ num_maps, pin_name,
+ cfg, ncfg,
+ PIN_MAP_TYPE_CONFIGS_PIN);
+ if (ret < 0)
+ goto free_cfgs;
+ };
+
+free_cfgs:
+ kfree(cfgs);
+ return ret;
+}
+
+static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np_config,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+
+{
+ unsigned int reserved_maps;
+ int ret;
+
+ reserved_maps = 0;
+ *map = NULL;
+ *num_maps = 0;
+
+ for_each_available_child_of_node_scoped(np_config, np) {
+ ret = pinctrl_scmi_imx_dt_group_node_to_map(pctldev, np, map,
+ &reserved_maps,
+ num_maps,
+ np_config->name);
+ if (ret < 0) {
+ pinctrl_utils_free_map(pctldev, *map, *num_maps);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinctrl_ops pinctrl_scmi_imx_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = pinctrl_scmi_imx_dt_node_to_map,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int pinctrl_scmi_imx_func_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int selector, unsigned int group)
+{
+ /*
+ * For i.MX SCMI PINCTRL , postpone the mux setting
+ * until config is set as they can be set together
+ * in one IPC call
+ */
+ return 0;
+}
+
+static const struct pinmux_ops pinctrl_scmi_imx_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = pinctrl_scmi_imx_func_set_mux,
+};
+
+static int pinctrl_scmi_imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ int ret;
+ struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param config_type;
+ u32 mask, val, shift;
+ u32 config_value;
+
+ if (!config)
+ return -EINVAL;
+
+ config_type = pinconf_to_config_param(*config);
+
+ ret = pinctrl_scmi_imx_map_pinconf_type(config_type, &mask, &shift);
+ if (ret)
+ return ret;
+
+ ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE,
+ IMX_SCMI_PIN_CONFIG, &val);
+ /* Convert SCMI error code to PINCTRL expected error code */
+ if (ret == -EOPNOTSUPP)
+ return -ENOTSUPP;
+ if (ret)
+ return ret;
+
+ config_value = (val & mask) >> shift;
+ *config = pinconf_to_config_packed(config_type, config_value);
+
+ dev_dbg(pmx->dev, "pin:%s, conf:0x%x, type: %d, val: %u",
+ pin_get_name(pctldev, pin), val, config_type, config_value);
+
+ return 0;
+}
+
+static int pinctrl_scmi_imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS];
+ u32 config_value[SCMI_NUM_CONFIGS];
+ enum scmi_pinctrl_conf_type *p_config_type = config_type;
+ u32 *p_config_value = config_value;
+ int ret;
+ int i;
+
+ if (!configs || !num_configs)
+ return -EINVAL;
+
+ if (num_configs > SCMI_NUM_CONFIGS) {
+ dev_err(pmx->dev, "num_configs(%d) too large\n", num_configs);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_configs; i++) {
+ /* cast to avoid build warning */
+ p_config_type[i] =
+ (enum scmi_pinctrl_conf_type)pinconf_to_config_param(configs[i]);
+ p_config_value[i] = pinconf_to_config_argument(configs[i]);
+
+ dev_err(pmx->dev, "pin: %u, type: %u, val: 0x%x\n",
+ pin, p_config_type[i], p_config_value[i]);
+ }
+
+ ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
+ p_config_type, p_config_value);
+ if (ret)
+ dev_err(pmx->dev, "Error set config %d\n", ret);
+
+ return ret;
+}
+
+static const struct pinconf_ops pinctrl_scmi_imx_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = pinctrl_scmi_imx_pinconf_get,
+ .pin_config_set = pinctrl_scmi_imx_pinconf_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
+static int scmi_pinctrl_imx_parse_groups(struct device_node *np,
+ struct pingroup *grp,
+ struct scmi_pinctrl_imx *pmx)
+{
+ const __be32 *p;
+ struct device *dev;
+ struct property *prop;
+ unsigned int *pins;
+ int npins;
+ u32 i = 0, pinmux;
+
+ dev = pmx->dev;
+
+ dev_dbg(dev, "group: %pOFn\n", np);
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ npins = of_property_count_elems_of_size(np, "pinmux", sizeof(u32));
+ if (npins < 0) {
+ dev_err(dev, "Failed to read 'pinmux' property in node %s.\n",
+ grp->name);
+ return npins;
+ }
+ if (!npins) {
+ dev_err(dev, "The group %s has no pins.\n", grp->name);
+ return -EINVAL;
+ }
+
+ grp->npins = npins;
+
+ pins = devm_kcalloc(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ i = 0;
+ of_property_for_each_u32(np, "pinmux", prop, p, pinmux) {
+ pins[i] = get_pin_no(pinmux);
+ dev_dbg(pmx->dev, "pin reg: 0x%x", pins[i] * 4);
+ i++;
+ }
+
+ grp->pins = pins;
+
+ return 0;
+}
+
+static int scmi_pinctrl_imx_parse_functions(struct device_node *np,
+ struct scmi_pinctrl_imx *pmx,
+ u32 index)
+{
+ struct pinfunction *func;
+ struct pingroup *grp;
+ const char **groups;
+ u32 i = 0;
+ int ret = 0;
+
+ dev_dbg(pmx->dev, "parse function(%u): %pOFn\n", index, np);
+
+ func = &pmx->functions[index];
+
+ /* Initialise function */
+ func->name = np->name;
+ func->ngroups = of_get_child_count(np);
+ if (func->ngroups == 0) {
+ dev_err(pmx->dev, "no groups defined in %pOF\n", np);
+ return -EINVAL;
+ }
+
+ groups = devm_kcalloc(pmx->dev, func->ngroups, sizeof(*func->groups),
+ GFP_KERNEL);
+ if (!groups)
+ return -ENOMEM;
+
+ for_each_child_of_node_scoped(np, child) {
+ groups[i] = child->name;
+ grp = &pmx->groups[pmx->grp_index++];
+ ret = scmi_pinctrl_imx_parse_groups(child, grp, pmx);
+ if (ret)
+ return ret;
+ i++;
+ }
+
+ func->groups = groups;
+
+ return 0;
+}
+
+static int scmi_pinctrl_imx_probe_dt(struct scmi_device *sdev,
+ struct scmi_pinctrl_imx *pmx)
+{
+ int i, ret, nfuncs;
+ struct device_node *np = sdev->dev.of_node;
+
+ pmx->dev = &sdev->dev;
+
+ nfuncs = of_get_child_count(np);
+ if (nfuncs <= 0) {
+ dev_err(&sdev->dev, "no functions defined\n");
+ return -EINVAL;
+ }
+
+ pmx->nfunctions = nfuncs;
+ pmx->functions = devm_kcalloc(&sdev->dev, nfuncs,
+ sizeof(*pmx->functions), GFP_KERNEL);
+ if (!pmx->functions)
+ return -ENOMEM;
+
+ pmx->ngroups = 0;
+ for_each_child_of_node_scoped(np, child)
+ pmx->ngroups += of_get_child_count(child);
+
+ pmx->groups = devm_kcalloc(&sdev->dev, pmx->ngroups,
+ sizeof(*pmx->groups), GFP_KERNEL);
+ if (!pmx->groups)
+ return -ENOMEM;
+
+ i = 0;
+ for_each_child_of_node_scoped(np, child) {
+ ret = scmi_pinctrl_imx_parse_functions(child, pmx, i++);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int
+scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *desc)
+{
+ struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ int ret, i;
+
+ npins = pmx->ops->count_get(pmx->ph, PIN_TYPE);
+ pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < npins; i++) {
+ pins[i].number = i;
+ /* no need free name, firmware driver handles it */
+ ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
+ if (ret)
+ return dev_err_probe(pmx->dev, ret,
+ "Can't get name for pin %d", i);
+ }
+
+ desc->npins = npins;
+ desc->pins = pins;
+ dev_dbg(pmx->dev, "got pins %u", npins);
+
+ return 0;
+}
+
+static const char * const scmi_pinctrl_imx_allowlist[] = {
+ "fsl,imx95",
+ NULL
+};
+
+static int scmi_pinctrl_imx_probe(struct scmi_device *sdev)
+{
+ struct device *dev = &sdev->dev;
+ const struct scmi_handle *handle = sdev->handle;
+ struct scmi_pinctrl_imx *pmx;
+ struct scmi_protocol_handle *ph;
+ const struct scmi_pinctrl_proto_ops *pinctrl_ops;
+ int ret;
+
+ if (!handle)
+ return -EINVAL;
+
+ if (!of_machine_compatible_match(scmi_pinctrl_imx_allowlist))
+ return -ENODEV;
+
+ pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph);
+ if (IS_ERR(pinctrl_ops))
+ return PTR_ERR(pinctrl_ops);
+
+ pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
+ if (!pmx)
+ return -ENOMEM;
+
+ pmx->ph = ph;
+ pmx->ops = pinctrl_ops;
+
+ pmx->dev = dev;
+ pmx->pctl_desc.name = DRV_NAME;
+ pmx->pctl_desc.owner = THIS_MODULE;
+ pmx->pctl_desc.pctlops = &pinctrl_scmi_imx_pinctrl_ops;
+ pmx->pctl_desc.pmxops = &pinctrl_scmi_imx_pinmux_ops;
+ pmx->pctl_desc.confops = &pinctrl_scmi_imx_pinconf_ops;
+
+ ret = scmi_pinctrl_imx_get_pins(pmx, &pmx->pctl_desc);
+ if (ret)
+ return ret;
+
+ ret = scmi_pinctrl_imx_probe_dt(sdev, pmx);
+ if (ret)
+ return ret;
+
+ ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
+ &pmx->pctldev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
+
+ return pinctrl_enable(pmx->pctldev);
+}
+
+static const struct scmi_device_id scmi_id_table[] = {
+ { SCMI_PROTOCOL_PINCTRL, "pinctrl-imx" },
+ { }
+};
+MODULE_DEVICE_TABLE(scmi, scmi_id_table);
+
+static struct scmi_driver scmi_pinctrl_imx_driver = {
+ .name = DRV_NAME,
+ .probe = scmi_pinctrl_imx_probe,
+ .id_table = scmi_id_table,
+};
+module_scmi_driver(scmi_pinctrl_imx_driver);
+
+MODULE_AUTHOR("Peng Fan <peng.fan at nxp.com>");
+MODULE_DESCRIPTION("i.MX SCMI pin controller driver");
+MODULE_LICENSE("GPL");
--
2.37.1
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